From 5a4b106f98545c1593fa7104fc526c3bf6123698 Mon Sep 17 00:00:00 2001 From: Pavel Pisa Date: Fri, 8 Feb 2019 19:11:45 +0100 Subject: Accept SINC and SINCI instructions and flush even instruction cache on CACHE opcode. Because individual cache maintenance operations are not decoded, be on safe side and flush all caches when CACHE operation is processed, Signed-off-by: Pavel Pisa --- qtmips_machine/instruction.cpp | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'qtmips_machine/instruction.cpp') diff --git a/qtmips_machine/instruction.cpp b/qtmips_machine/instruction.cpp index 694a32d..ad4ded3 100644 --- a/qtmips_machine/instruction.cpp +++ b/qtmips_machine/instruction.cpp @@ -111,7 +111,8 @@ static const struct InstructionMap alu_instruction_map[] = { {"BREAK", IT_R, ALU_OP_BREAK, NOMEM, nullptr, .flags = IMF_SUPPORTED | IMF_EXCEPTION}, IM_UNKNOWN, - IM_UNKNOWN, + {"SYNC", IT_I, NOALU, NOMEM, nullptr, // SYNC + .flags = IMF_SUPPORTE}, {"MFHI", IT_R, ALU_OP_MFHI, NOMEM, nullptr, .flags = FLAGS_ALU_T_R_D | IMF_READ_HILO}, {"MTHI", IT_R, ALU_OP_MTHI, NOMEM, nullptr, @@ -276,7 +277,7 @@ static const struct InstructionMap regimm_instruction_map[] = { IM_UNKNOWN, IM_UNKNOWN, {"SYNCI", IT_I, NOALU, NOMEM, nullptr, // SYNCI - .flags = IMF_SUPPORTED | IMF_BJR_REQ_RS}, + .flags = IMF_SUPPORTE}, }; const std::int32_t instruction_map_opcode_field = IMF_SUB_ENCODE(6, 26); -- cgit v1.2.3