From 15dbd208fa6c1ac4dc0684c95c43cc40b2462cbf Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Karel=20Ko=C4=8D=C3=AD?= Date: Sun, 8 Apr 2018 11:55:52 +0200 Subject: Integrate cache with rest of the machine core --- qtmips_machine/core.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'qtmips_machine/core.h') diff --git a/qtmips_machine/core.h b/qtmips_machine/core.h index a0bc2a2..98f3e4a 100644 --- a/qtmips_machine/core.h +++ b/qtmips_machine/core.h @@ -14,7 +14,7 @@ namespace machine { class Core : public QObject { Q_OBJECT public: - Core(Registers *regs, MemoryAccess *mem); + Core(Registers *regs, MemoryAccess *mem_program, MemoryAccess *mem_data); virtual void step() = 0; // Do single step @@ -30,7 +30,7 @@ signals: protected: Registers *regs; - MemoryAccess *mem; + MemoryAccess *mem_data, *mem_program; struct dtFetch { Instruction inst; // Loaded instruction @@ -80,7 +80,7 @@ protected: class CoreSingle : public Core { public: - CoreSingle(Registers *regs, MemoryAccess *mem, bool jmp_delay_slot); + CoreSingle(Registers *regs, MemoryAccess *mem_program, MemoryAccess *mem_data, bool jmp_delay_slot); ~CoreSingle(); void step(); @@ -93,7 +93,7 @@ private: class CorePipelined : public Core { public: - CorePipelined(Registers *regs, MemoryAccess *mem, enum MachineConfig::HazardUnit hazard_unit = MachineConfig::HU_STALL_FORWARD); + CorePipelined(Registers *regs, MemoryAccess *mem_program, MemoryAccess *mem_data, enum MachineConfig::HazardUnit hazard_unit = MachineConfig::HU_STALL_FORWARD); void step(); -- cgit v1.2.3