From 789186fd63fb3fb63af1d8875cbe43609321b9d8 Mon Sep 17 00:00:00 2001 From: Pavel Pisa Date: Fri, 8 Feb 2019 13:52:59 +0100 Subject: Implement LL and SC as simple load and store word. SC returns 1 unconditionally. Signed-off-by: Pavel Pisa --- qtmips_machine/core.cpp | 17 +++++++++++++---- 1 file changed, 13 insertions(+), 4 deletions(-) (limited to 'qtmips_machine/core.cpp') diff --git a/qtmips_machine/core.cpp b/qtmips_machine/core.cpp index 4164db0..2d33309 100644 --- a/qtmips_machine/core.cpp +++ b/qtmips_machine/core.cpp @@ -264,10 +264,19 @@ struct Core::dtMemory Core::memory(const struct dtExecute &dt) { } else { if (dt.memctl == AC_CACHE_OP) mem_data->sync(); - else if (memwrite) - mem_data->write_ctl(dt.memctl, mem_addr, dt.val_rt); - else if (memread) - towrite_val = mem_data->read_ctl(dt.memctl, mem_addr); + else if (memwrite) { + if (dt.memctl == AC_STORE_CONDITIONAL) { + mem_data->write_ctl(AC_WORD, mem_addr, dt.val_rt); + towrite_val = 1; + } else { + mem_data->write_ctl(dt.memctl, mem_addr, dt.val_rt); + } + } else if (memread) { + if (dt.memctl == AC_LOAD_LINKED) + towrite_val = mem_data->read_ctl(AC_WORD, mem_addr); + else + towrite_val = mem_data->read_ctl(dt.memctl, mem_addr); + } } emit memory_alu_value(dt.alu_val); -- cgit v1.2.3