From 73886d9d1733368fe3c876c8e613ba5821e12944 Mon Sep 17 00:00:00 2001 From: Pavel Pisa Date: Mon, 4 Mar 2019 22:38:34 +0100 Subject: Use irq 3 (HW1) for Rx and irq 2 (HW0) for Tx to be compatible with SPIM. Jump to address 0x8000180 by default and to EBase + 0x180 when EBase is set to be compatible with real MIPS CPU. Signed-off-by: Pavel Pisa --- qtmips_machine/core.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'qtmips_machine/core.cpp') diff --git a/qtmips_machine/core.cpp b/qtmips_machine/core.cpp index 22dfdc8..351ffb0 100644 --- a/qtmips_machine/core.cpp +++ b/qtmips_machine/core.cpp @@ -141,7 +141,7 @@ bool Core::handle_exception(Core *core, Registers *regs, ExceptionCause excause, if (cop0state->read_cop0reg(Cop0State::EBase) != 0) { if (excause == EXCAUSE_INT) { cop0state->set_status_exl(true); - regs->pc_abs_jmp(cop0state->read_cop0reg(Cop0State::EBase)); + regs->pc_abs_jmp(cop0state->exception_pc_address()); } } } -- cgit v1.2.3