From 68f2af6801756980ec53347c0acb7fcc292f7939 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Karel=20Ko=C4=8D=C3=AD?= <cynerd@email.cz>
Date: Tue, 21 Nov 2017 13:17:18 +0100
Subject: Add list of all implemented instructions

---
 README.md       |   1 +
 instructions.md | 141 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 142 insertions(+)
 create mode 100644 instructions.md

diff --git a/README.md b/README.md
index 717c50e..53dbe0e 100644
--- a/README.md
+++ b/README.md
@@ -47,3 +47,4 @@ being so.
   annoying for users so difference between cache and memory is just in collected
   statistics)
 * Interrupts and exceptions (if exception occurs then machine execution is halted)
+* Branch-likeli instructions (they are marked as obsolete)
diff --git a/instructions.md b/instructions.md
new file mode 100644
index 0000000..ccc16bc
--- /dev/null
+++ b/instructions.md
@@ -0,0 +1,141 @@
+Instructions
+============
+This is list of all MIPS1 instructions and their implementation status in QtMips.
+
+CPU Arithmetic Instruction
+--------------------------
+* [ ] ADD
+* [ ] ADDI
+* [ ] ADDIU
+* [ ] ADDU
+* [ ] CLO
+* [ ] CLZ
+* [ ] DIV
+* [ ] DIVU
+* [ ] MADD
+* [ ] MADDU
+* [ ] MSUB
+* [ ] MSUBU
+* [ ] MUL
+* [ ] MULT
+* [ ] MULTU
+* [ ] SLT
+* [ ] SLTI
+* [ ] SLTIU
+* [ ] SLTU
+* [ ] SUB
+* [ ] SUBU
+
+CPU Branch and Jump Instructions
+--------------------------------
+* [ ] B
+* [ ] BAL
+* [ ] BEQ
+* [ ] BGEZ
+* [ ] BGEZAL
+* [ ] BGTZ
+* [ ] BLEZ
+* [ ] BLTZ
+* [ ] BLTZAL
+* [ ] BNE
+* [ ] J
+* [ ] JAL
+* [ ] JALR
+* [ ] JR
+
+CPU Instruction Control Instruction
+-----------------------------------
+* [ ] NOP
+* [ ] SSNOP
+
+CPU Load, Store and Memory Control Instructions
+-----------------------------------------------
+* [ ] LB
+* [ ] LBU
+* [ ] LH
+* [ ] LHU
+* [ ] LL
+* [ ] LW
+* [ ] LWL
+* [ ] LWR
+* [ ] PREF
+* [ ] SB
+* [ ] SC
+* [ ] SD
+* [ ] SH
+* [ ] SW
+* [ ] SWL
+* [ ] SWR
+* [ ] SYNC
+
+CPU Logical Instructions
+------------------------
+* [ ] AND
+* [ ] ANDI
+* [ ] LUI
+* [ ] NOR
+* [ ] OR
+* [ ] ORI
+* [ ] XOR
+* [ ] XORI
+
+CPU Move Instruction
+--------------------
+* [ ] MFHI
+* [ ] MFLO
+* [ ] MTHI
+* [ ] MTHO
+* [ ] MOVN
+* [ ] MOVZ
+* MOVF, MOVT won't be implemented as floating coprocessor won't be implemented
+
+CPU Shift Instructions
+----------------------
+* [ ] SLL
+* [ ] SLLV
+* [ ] SRA
+* [ ] SRAV
+* [ ] SRL
+* [ ] SRLV
+
+CPU Trap Instructions
+---------------------
+Following instruction will be implemented but only as dummy ones as we are not
+implementing privileged instructions. They will all result to exception and core
+execution stop.
+
+* [ ] BREAK
+* [ ] TEQ
+* [ ] TEQI
+* [ ] TGE
+* [ ] TGEI
+* [ ] TGEIU
+* [ ] TGEU
+* [ ] TLT
+* [ ] TLTI
+* [ ] TLTIU
+* [ ] TLTU
+* [ ] TNE
+* [ ] TNEI
+* SYSCALL won't be implemented at all
+
+Obsolete CPU branch instructions
+--------------------------------
+None of these instructions will be implemented as they are marked as obsolete and
+they shouldn't be used by compiler and the same way by programmers.
+
+FPU Instructions
+----------------
+No FPU instruction will be implemented as no FPU is planned to be implemented.
+
+Coprocessor Instructions
+------------------------
+None of these will be implemented as coprocessor 2 won't be implemented.
+
+Privileged instructions
+-----------------------
+None of these will be implemented as privileged state won't be implemented.
+
+EJTAG Instructions
+------------------
+No instruction will be implemented as no ejtag support.
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