qtmips - MIPS CPU emulator for education purposes

	Commit message (Collapse)	Author	Age
*	Allow byte and half-word access to the peripherals.	Pavel Pisa	2019-03-13
\| \| \| \|	Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
*	Use irq 3 (HW1) for Rx and irq 2 (HW0) for Tx to be compatible with SPIM.	Pavel Pisa	2019-03-04
\| \| \| \| \| \| \|	Jump to address 0x8000180 by default and to EBase + 0x180 when EBase is set to be compatible with real MIPS CPU. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
*	Implemented interrupt delivery and processing for serial port.	Pavel Pisa	2019-03-04
\| \| \| \|	Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
*	Simple serial port receive implementation.	Pavel Pisa	2019-02-25
\| \| \| \| \| \| \| \| \|	Simple polled mode serial port input implemented for serial port peripheral and for read and readv system calls. When end of input character reserve is reached for read/readv, newline is automatically appended. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
*	Change serial port peripheral to match SPIM registers definition.	Pavel Pisa	2019-02-25
\| \| \| \| \| \| \|	Still Tx only and keep 0xffffc000 base to allows single instruction LW and SW access. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
*	Include simple serial port terminal and prepare empty peripheral dock.	Pavel Pisa	2019-02-13
	Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>