| Commit message (Collapse) | Author | Age |
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Instruction parsing is rough and does not support branch offset computation.
Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
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breakpoint for first cycle after resume.
Instruction for stage is updated when given stage is flushed as well.
But other signals are left intact, it is duty of memory stage
to discard effect of instruction causing interrupt.
Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
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It works like real inserted breakpoint on hardware.
Breakpoint has to be removed to allow code continue
because else instruction is refetch and breakpoint
triggers again. The single step function should
resolve temporal masking of the breakpoint.
Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
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stages.
Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
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Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
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Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
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Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
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Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
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Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
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Added machine status.
Widgets now hold size and registers dock has now scrollbars.
And more...
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Well I should commit every change instead of this madness. I am not
documenting changes as all this is just improvements and implementation
progression.
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Adding work done so far.
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