| Commit message (Collapse) | Author | Age |
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This allows to specify requirement for RS and RD on instruction
basis even for T_R / ALU instructions.
Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
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When any variant of cache instruction is detected
flush and invalidate whole data cache.
Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
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Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
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Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
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They are not implemented and even if they would they usage would be
little bit funky as they would jump by internal amount of page memory.
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These are just code fixes. Shouldn't change anything but makes code
cleaner.
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This functions can be used to write or read 32bit values from memory and
memory on its own does signextends for example depending on passed
control value.
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For core testing we want to compare whole memory and registers.
Registers are pretty simple but in case of memory it is some what more
complicated and required its own tests to be sure that it works.
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Adding work done so far.
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