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* Implement realistic hazard resolution for JR, JALR, BEQ, BNE, BLTZ, BGEZ ↵Pavel Pisa2019-02-02
| | | | | | | | | | | instructions. The previous code worked by chance only because decode has been fully processed including forwarding from M and W before PC processing started. But in real hardware the PC processing runs in parallel with ALU and cannot read its results in the same cycle. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Include support for JALR support.Pavel Pisa2019-01-31
| | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Initial support for JAL.Pavel Pisa2019-01-31
| | | | | | | The JR, BEQ, BNE are most probably incorrect still. There is missing forwarding for pipelined execution. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Display rs, rt, rd and write register number in all stages.Pavel Pisa2019-01-31
| | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Correct processing of ORI, ANDI, XORI instructions which require ↵Pavel Pisa2019-01-31
| | | | | | zero-extended immediate. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Do not replace rt by forward if instruction in T_R or store.Pavel Pisa2019-01-30
| | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Display execution stage forward signals in the view.Pavel Pisa2019-01-30
| | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Correct hazards processing.Pavel Pisa2019-01-30
| | | | | | | | The shorter loop has priority. This is achieved by later processing when it replaces possible result from longer loop over W stage. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Add few more labelsKarel Kočí2018-05-24
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* Add buses statis viewsKarel Kočí2018-05-24
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* Fix load and store instructionsKarel Kočí2018-05-02
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* Implement LUIKarel Kočí2018-04-08
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* Implement sync for memoryKarel Kočí2018-04-08
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* Integrate cache with rest of the machine coreKarel Kočí2018-04-08
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* Fix forwarding checker for I and J and S* instructionsKarel Kočí2018-03-06
| | | | THere are exceptions when we care about forwarding and when we don't.
* Forward from execute stage to decode stage latchKarel Kočí2018-02-14
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* Do empty fetch stage to report fetch even if we stallKarel Kočí2018-02-14
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* Fix signextend in coreKarel Kočí2018-02-14
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* Add instruction view to single coreKarel Kočí2018-01-21
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* Cleanup some todos in codeKarel Kočí2018-01-15
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* Implement hazard unitKarel Kočí2018-01-15
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* Allow instruction trace from any stageKarel Kočí2018-01-11
| | | | | | In reality this internally allows us to see stages even it we are not using pipelining but that is hidden from outside simply to not confuse user.
* Implement machine restartKarel Kočí2018-01-05
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* Allow delay slot disable for non-pipelined coreKarel Kočí2018-01-03
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* Add trace-feth to qtmips_cliKarel Kočí2018-01-03
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* Put qtmips_machine to machine namespaceKarel Kočí2017-12-17
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* Implement some store and load instructionsKarel Kočí2017-12-12
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* Fix immediate alu operationKarel Kočí2017-12-12
| | | | | There should be a sign extension to 32bit when doing immediate operations.
* Implement branch and jump instructionsKarel Kočí2017-12-12
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* Add crude implementation of MOV* instructionsKarel Kočí2017-11-25
| | | | I don't like how it's implemented but I have no other idea atm.
* Implement instructions for moving from and to HI and LO registersKarel Kočí2017-11-25
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* Test pipelined coreKarel Kočí2017-11-25
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* Implement some logical operationsKarel Kočí2017-11-21
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* Implement some immediate arithmetic instructionsKarel Kočí2017-11-21
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* Implement and test ADDKarel Kočí2017-11-21
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* Another huge pile of work for about two monthsKarel Kočí2017-11-19
| | | | | | Well I should commit every change instead of this madness. I am not documenting changes as all this is just improvements and implementation progression.
* Initial commitKarel Kočí2017-08-30
Adding work done so far.
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