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qtmips
fix-memory-view
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MIPS CPU emulator for education purposes
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qtmips_machine
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core.cpp
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Age
...
*
Implement realistic hazard resolution for JR, JALR, BEQ, BNE, BLTZ, BGEZ inst...
Pavel Pisa
2019-02-02
*
Include support for JALR support.
Pavel Pisa
2019-01-31
*
Initial support for JAL.
Pavel Pisa
2019-01-31
*
Display rs, rt, rd and write register number in all stages.
Pavel Pisa
2019-01-31
*
Correct processing of ORI, ANDI, XORI instructions which require zero-extende...
Pavel Pisa
2019-01-31
*
Do not replace rt by forward if instruction in T_R or store.
Pavel Pisa
2019-01-30
*
Display execution stage forward signals in the view.
Pavel Pisa
2019-01-30
*
Correct hazards processing.
Pavel Pisa
2019-01-30
*
Add few more labels
Karel Kočí
2018-05-24
*
Add buses statis views
Karel Kočí
2018-05-24
*
Fix load and store instructions
Karel Kočí
2018-05-02
*
Implement LUI
Karel Kočí
2018-04-08
*
Implement sync for memory
Karel Kočí
2018-04-08
*
Integrate cache with rest of the machine core
Karel Kočí
2018-04-08
*
Fix forwarding checker for I and J and S* instructions
Karel Kočí
2018-03-06
*
Forward from execute stage to decode stage latch
Karel Kočí
2018-02-14
*
Do empty fetch stage to report fetch even if we stall
Karel Kočí
2018-02-14
*
Fix signextend in core
Karel Kočí
2018-02-14
*
Add instruction view to single core
Karel Kočí
2018-01-21
*
Cleanup some todos in code
Karel Kočí
2018-01-15
*
Implement hazard unit
Karel Kočí
2018-01-15
*
Allow instruction trace from any stage
Karel Kočí
2018-01-11
*
Implement machine restart
Karel Kočí
2018-01-05
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Allow delay slot disable for non-pipelined core
Karel Kočí
2018-01-03
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Add trace-feth to qtmips_cli
Karel Kočí
2018-01-03
*
Put qtmips_machine to machine namespace
Karel Kočí
2017-12-17
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Implement some store and load instructions
Karel Kočí
2017-12-12
*
Fix immediate alu operation
Karel Kočí
2017-12-12
*
Implement branch and jump instructions
Karel Kočí
2017-12-12
*
Add crude implementation of MOV* instructions
Karel Kočí
2017-11-25
*
Implement instructions for moving from and to HI and LO registers
Karel Kočí
2017-11-25
*
Test pipelined core
Karel Kočí
2017-11-25
*
Implement some logical operations
Karel Kočí
2017-11-21
*
Implement some immediate arithmetic instructions
Karel Kočí
2017-11-21
*
Implement and test ADD
Karel Kočí
2017-11-21
*
Another huge pile of work for about two months
Karel Kočí
2017-11-19
*
Initial commit
Karel Kočí
2017-08-30
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