| Commit message (Collapse) | Author | Age | |
|---|---|---|---|
| * | Remove dependency of ALU operation encoding on MIPS instruction format. | Pavel Pisa | 2019-02-07 |
| | | | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> | ||
| * | Implemented base for exception handling. | Pavel Pisa | 2019-02-06 |
| | | | | | | | | | | | | | | | Memory stage is chosen to be exception commit stage. Instructions flow postponed and stages holding following instructions are cleaned. Processing of syscall at decode stage as jump to the handler would be better solution in real hardware but for future emulated syscalls it is better to reach consistent state of registers. Memory access caused exceptions would require cleanup even in real hardware. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> | ||
| * | Resolve some memory leaks found by Valgrind. | Pavel Pisa | 2019-02-06 |
| | | | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> | ||
| * | Reorganize PC handling and implement full REGIMM decode. | Pavel Pisa | 2019-02-05 |
| | | | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> | ||
| * | Correct shift operation and make ALU_OP_MOVZ and ALU_OP_MOVN encoding ↵ | Pavel Pisa | 2019-02-05 |
| | | | | | | | independent. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> | ||
| * | Rewrite instruction decoding to be generic and mostly architecture independent. | Pavel Pisa | 2019-02-05 |
| | | | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> | ||
| * | Remove almost all direct access to opcode and function from the core. | Pavel Pisa | 2019-02-04 |
| | | | | | | | | Remaining are MOVZ and MOVN in the execution phase and all branch and jump operations in handle_pc(). Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> | ||
| * | Take into account actual requirements for rs, rt and rd write for individual ↵ | Pavel Pisa | 2019-02-04 |
| | | | | | | | instructions. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> | ||
| * | Unified instructions table and access type move to machinedefs.h . | Pavel Pisa | 2019-02-04 |
| | | | | | | | | This allows to specify requirement for RS and RD on instruction basis even for T_R / ALU instructions. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> | ||
| * | Primitive implementation of cache instruction. | Pavel Pisa | 2019-02-04 |
| | | | | | | | | When any variant of cache instruction is detected flush and invalidate whole data cache. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> | ||
| * | Add license to the source files. | Pavel Pisa | 2019-02-04 |
| | | | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> | ||
| * | Implement BREAK instruction to stop continuous execution. | Pavel Pisa | 2019-02-03 |
| | | | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> | ||
| * | Implement instructions MULT, MULTU, DIV, DIVU. | Pavel Pisa | 2019-02-03 |
| | | | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> | ||
| * | Implement realistic hazard resolution for JR, JALR, BEQ, BNE, BLTZ, BGEZ ↵ | Pavel Pisa | 2019-02-02 |
| | | | | | | | | | | | | instructions. The previous code worked by chance only because decode has been fully processed including forwarding from M and W before PC processing started. But in real hardware the PC processing runs in parallel with ALU and cannot read its results in the same cycle. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> | ||
| * | Include support for JALR support. | Pavel Pisa | 2019-01-31 |
| | | | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> | ||
| * | Initial support for JAL. | Pavel Pisa | 2019-01-31 |
| | | | | | | | | The JR, BEQ, BNE are most probably incorrect still. There is missing forwarding for pipelined execution. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> | ||
| * | Display rs, rt, rd and write register number in all stages. | Pavel Pisa | 2019-01-31 |
| | | | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> | ||
| * | Correct processing of ORI, ANDI, XORI instructions which require ↵ | Pavel Pisa | 2019-01-31 |
| | | | | | | | zero-extended immediate. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> | ||
| * | Do not replace rt by forward if instruction in T_R or store. | Pavel Pisa | 2019-01-30 |
| | | | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> | ||
| * | Display execution stage forward signals in the view. | Pavel Pisa | 2019-01-30 |
| | | | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> | ||
| * | Correct hazards processing. | Pavel Pisa | 2019-01-30 |
| | | | | | | | | | The shorter loop has priority. This is achieved by later processing when it replaces possible result from longer loop over W stage. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> | ||
| * | Add few more labels | Karel Kočí | 2018-05-24 |
| | | |||
| * | Add buses statis views | Karel Kočí | 2018-05-24 |
| | | |||
| * | Fix load and store instructions | Karel Kočí | 2018-05-02 |
| | | |||
| * | Implement LUI | Karel Kočí | 2018-04-08 |
| | | |||
| * | Implement sync for memory | Karel Kočí | 2018-04-08 |
| | | |||
| * | Integrate cache with rest of the machine core | Karel Kočí | 2018-04-08 |
| | | |||
| * | Fix forwarding checker for I and J and S* instructions | Karel Kočí | 2018-03-06 |
| | | | | | THere are exceptions when we care about forwarding and when we don't. | ||
| * | Forward from execute stage to decode stage latch | Karel Kočí | 2018-02-14 |
| | | |||
| * | Do empty fetch stage to report fetch even if we stall | Karel Kočí | 2018-02-14 |
| | | |||
| * | Fix signextend in core | Karel Kočí | 2018-02-14 |
| | | |||
| * | Add instruction view to single core | Karel Kočí | 2018-01-21 |
| | | |||
| * | Cleanup some todos in code | Karel Kočí | 2018-01-15 |
| | | |||
| * | Implement hazard unit | Karel Kočí | 2018-01-15 |
| | | |||
| * | Allow instruction trace from any stage | Karel Kočí | 2018-01-11 |
| | | | | | | | In reality this internally allows us to see stages even it we are not using pipelining but that is hidden from outside simply to not confuse user. | ||
| * | Implement machine restart | Karel Kočí | 2018-01-05 |
| | | |||
| * | Allow delay slot disable for non-pipelined core | Karel Kočí | 2018-01-03 |
| | | |||
| * | Add trace-feth to qtmips_cli | Karel Kočí | 2018-01-03 |
| | | |||
| * | Put qtmips_machine to machine namespace | Karel Kočí | 2017-12-17 |
| | | |||
| * | Implement some store and load instructions | Karel Kočí | 2017-12-12 |
| | | |||
| * | Fix immediate alu operation | Karel Kočí | 2017-12-12 |
| | | | | | | There should be a sign extension to 32bit when doing immediate operations. | ||
| * | Implement branch and jump instructions | Karel Kočí | 2017-12-12 |
| | | |||
| * | Add crude implementation of MOV* instructions | Karel Kočí | 2017-11-25 |
| | | | | | I don't like how it's implemented but I have no other idea atm. | ||
| * | Implement instructions for moving from and to HI and LO registers | Karel Kočí | 2017-11-25 |
| | | |||
| * | Test pipelined core | Karel Kočí | 2017-11-25 |
| | | |||
| * | Implement some logical operations | Karel Kočí | 2017-11-21 |
| | | |||
| * | Implement some immediate arithmetic instructions | Karel Kočí | 2017-11-21 |
| | | |||
| * | Implement and test ADD | Karel Kočí | 2017-11-21 |
| | | |||
| * | Another huge pile of work for about two months | Karel Kočí | 2017-11-19 |
| | | | | | | | Well I should commit every change instead of this madness. I am not documenting changes as all this is just improvements and implementation progression. | ||
| * | Initial commit | Karel Kočí | 2017-08-30 |
| Adding work done so far. | |||
 |
index : qtmips | |
| MIPS CPU emulator for education purposes | Gitolite user |
| aboutsummaryrefslogtreecommitdiff |