| Commit message (Collapse) | Author | Age |
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Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
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Instructions description in instruction.cpp has been
pragmatically augmented by tool based on Python MIPS simulator,
hazards analyzer
https://github.com/ppisa/apo-simarch
That code has been originally distilled from from GNU
binutils sources.
Implementation is now inline with my original proposal
Previous solution gets untenable with more complex
instructions and its complexity would grow extremely.
MIPS instruction set with coprocessor instructions
which use sel field, rd used as index, rt as destination
and other peculiarities in newer versions cannot
be processed based on basic CPU control signals.
Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
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Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
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Jump to address 0x8000180 by default and to EBase + 0x180
when EBase is set to be compatible with real MIPS CPU.
Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
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Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
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Simple polled mode serial port input implemented for
serial port peripheral and for read and readv system
calls. When end of input character reserve is reached
for read/readv, newline is automatically appended.
Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
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This allows simple visual compare of rs and rt in execution stage
with register number to be written in memory and write-back stages.
Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
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Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
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Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
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Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
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Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
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Add into cache statistic number of backing/main memory accesses.
Correction of meaning and computation of the cache statistic.
Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
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Windows builds.
Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
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Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
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Enable number of columns computation even for invisible QLabels
to restore wide registers dock with multiple columns instead
of only one.
Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
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Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
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Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
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Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
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Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
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Signed value caused in the conversion incorrect behavior
for some corner cases.
Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
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Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
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part of address-space on 32-bit systems.
Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
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longer.
Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
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Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
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Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
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Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
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The value is forced to change one step down and then up.
Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
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Tested with code compiled by Linux PIC based GCC compiler
with calling musl-libc sprintf function.
Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
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Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
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peripherals.
Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
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Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
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Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
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Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
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static machine lib.
Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
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Instruction parsing is rough and does not support branch offset computation.
Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
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without disturbing statistic.
This allows to switch view between CPU and raw memory content.
Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
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breakpoint for first cycle after resume.
Instruction for stage is updated when given stage is flushed as well.
But other signals are left intact, it is duty of memory stage
to discard effect of instruction causing interrupt.
Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
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It works like real inserted breakpoint on hardware.
Breakpoint has to be removed to allow code continue
because else instruction is refetch and breakpoint
triggers again. The single step function should
resolve temporal masking of the breakpoint.
Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
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Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
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Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
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Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
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Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
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Unfortunately, QModelIndex supports only integers for rows
and columns. Even if only size to maxint is used then
Qt engine crashes. Workaround for Qt limitations is material
for followup patches.
Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
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Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
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Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
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Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
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