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* Use trick to force knobs to resend signals when machine is newly connected.Pavel Pisa2019-02-13
| | | | | | The value is forced to change one step down and then up. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Implemented three dials equivalent to MZ_APO RGB dials.Pavel Pisa2019-02-13
| | | | | | | Tested with code compiled by Linux PIC based GCC compiler with calling musl-libc sprintf function. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Include simple serial port terminal and prepare empty peripheral dock.Pavel Pisa2019-02-13
| | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Add simple about dialog and prepare menu entries for serial port and ↵Pavel Pisa2019-02-13
| | | | | | peripherals. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Add speed option to run core for time chunks without visualization.Pavel Pisa2019-02-13
| | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* At least partial solution to depict forward paths to compare units/branches.Pavel Pisa2019-02-12
| | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Add signals and multiplexers for ALU inputs forwarding.Pavel Pisa2019-02-12
| | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Add ELF library even to the final executables linking to allow build with ↵Pavel Pisa2019-02-12
| | | | | | static machine lib. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Make memory and program listing editable.Pavel Pisa2019-02-12
| | | | | | Instruction parsing is rough and does not support branch offset computation. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Add debug access to rword and friends to allow read data through cache ↵Pavel Pisa2019-02-12
| | | | | | | | without disturbing statistic. This allows to switch view between CPU and raw memory content. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Display red background for instruction causing exception and skip HW ↵Pavel Pisa2019-02-11
| | | | | | | | | | breakpoint for first cycle after resume. Instruction for stage is updated when given stage is flushed as well. But other signals are left intact, it is duty of memory stage to discard effect of instruction causing interrupt. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Basic "hardware" breakpoints support implemented.Pavel Pisa2019-02-11
| | | | | | | | | | It works like real inserted breakpoint on hardware. Breakpoint has to be removed to allow code continue because else instruction is refetch and breakpoint triggers again. The single step function should resolve temporal masking of the breakpoint. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Extend program view to support selected stage followup.Pavel Pisa2019-02-11
| | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Converted program listing to be QTableView based.Pavel Pisa2019-02-11
| | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* QTableView based memory view is working.Pavel Pisa2019-02-11
| | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Implemented workaround QTableView limits workaround which mostly works.Pavel Pisa2019-02-10
| | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Memory QTableView working for part of the memory range.Pavel Pisa2019-02-10
| | | | | | | | | Unfortunately, QModelIndex supports only integers for rows and columns. Even if only size to maxint is used then Qt engine crashes. Workaround for Qt limitations is material for followup patches. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Next steps to implement QTableView based memory view.Pavel Pisa2019-02-10
| | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Correct MemoryDock header fields values.Fanda Vacek2019-02-09
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* Initial cleanup of MemoryDock as preparation for switch to QTableView.Pavel Pisa2019-02-09
| | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Correct build for LLVM.Fanda Vacek2019-02-09
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* View register numbers in decimal notation.Pavel Pisa2019-02-07
| | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Implemented simple indication of presence of memory location in the cache.Pavel Pisa2019-02-07
| | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Correct display of jump and branch instructions.Pavel Pisa2019-02-07
| | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Add address to emitted instruction to allow its use for branch address decoding.Pavel Pisa2019-02-07
| | | | | | | | The new Qt5 syntax is used to create connections because old syntax does not work with multiple arguments for some unresolved reason. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Implemented basic infrastructure to handle exceptions.Pavel Pisa2019-02-07
| | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Resolve some memory leaks found by Valgrind.Pavel Pisa2019-02-06
| | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Add license to the source files.Pavel Pisa2019-02-04
| | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Correct memory view updates for uncached and write-through case.Pavel Pisa2019-02-03
| | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Implement BREAK instruction to stop continuous execution.Pavel Pisa2019-02-03
| | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Implement realistic hazard resolution for JR, JALR, BEQ, BNE, BLTZ, BGEZ ↵Pavel Pisa2019-02-02
| | | | | | | | | | | instructions. The previous code worked by chance only because decode has been fully processed including forwarding from M and W before PC processing started. But in real hardware the PC processing runs in parallel with ALU and cannot read its results in the same cycle. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Initial support for JAL.Pavel Pisa2019-01-31
| | | | | | | The JR, BEQ, BNE are most probably incorrect still. There is missing forwarding for pipelined execution. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Display rs, rt, rd and write register number in all stages.Pavel Pisa2019-01-31
| | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Display execution stage forward signals in the view.Pavel Pisa2019-01-30
| | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Specify rpath during linking to find qtmips_machine library without install.Pavel Pisa2019-01-30
| | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Hide some values that shouldn't been visible in no pipelined versionKarel Kočí2018-06-20
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* Fix value position for non-pipelined coreKarel Kočí2018-05-24
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* Add few more labelsKarel Kočí2018-05-24
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* Add few additional labelsKarel Kočí2018-05-24
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* Add buses statis viewsKarel Kočí2018-05-24
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* Add cache view rendererKarel Kočí2018-05-23
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* Ignore hazard unit for nowKarel Kočí2018-05-23
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* Add cache statisticsKarel Kočí2018-05-23
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* Initial implementation of cache viewKarel Kočí2018-04-17
| | | | It needs some more work to look nice but it already works.
* Drop unneeded parameter from CoreViewScene constructorKarel Kočí2018-04-17
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* Fix angle scroll speedKarel Kočí2018-04-17
| | | | | I finally manage to make device to report as angle scroll device. And it was too fast scroll so I make it solver. It is now some what acceptable.
* Store memory and program view address positionKarel Kočí2018-04-17
| | | | | | This reloads memoryview with same base address as it was closed with. It somewhat works but with program view it seems to be buggy and shifts stuff down. But let's say that it's good enough for now.
* When changing focus load it back to edit field in memoryviewKarel Kočí2018-04-15
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* Add 2x speedKarel Kočí2018-04-15
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* Disable memory protection configuration fields for nowKarel Kočí2018-04-15
| | | | | Memory protection is not feature that is strictly required. Because of that it's implementation has lower priority.
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