| Commit message (Collapse) | Author | Age |
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Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
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Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
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Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
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Signed value caused in the conversion incorrect behavior
for some corner cases.
Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
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Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
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part of address-space on 32-bit systems.
Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
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longer.
Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
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Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
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Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
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Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
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The value is forced to change one step down and then up.
Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
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Tested with code compiled by Linux PIC based GCC compiler
with calling musl-libc sprintf function.
Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
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Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
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peripherals.
Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
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Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
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Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
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Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
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static machine lib.
Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
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Instruction parsing is rough and does not support branch offset computation.
Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
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without disturbing statistic.
This allows to switch view between CPU and raw memory content.
Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
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breakpoint for first cycle after resume.
Instruction for stage is updated when given stage is flushed as well.
But other signals are left intact, it is duty of memory stage
to discard effect of instruction causing interrupt.
Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
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It works like real inserted breakpoint on hardware.
Breakpoint has to be removed to allow code continue
because else instruction is refetch and breakpoint
triggers again. The single step function should
resolve temporal masking of the breakpoint.
Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
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Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
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Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
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Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
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Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
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Unfortunately, QModelIndex supports only integers for rows
and columns. Even if only size to maxint is used then
Qt engine crashes. Workaround for Qt limitations is material
for followup patches.
Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
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Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
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Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
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Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
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Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
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Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
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The new Qt5 syntax is used to create connections because
old syntax does not work with multiple arguments for some
unresolved reason.
Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
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Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
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Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
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Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
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Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
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Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
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instructions.
The previous code worked by chance only because decode has been fully
processed including forwarding from M and W before PC processing
started. But in real hardware the PC processing runs in parallel
with ALU and cannot read its results in the same cycle.
Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
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The JR, BEQ, BNE are most probably incorrect still.
There is missing forwarding for pipelined execution.
Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
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Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
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Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
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Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
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