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Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
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The labels are parsed and stored into symbol table
but expressions dependent on symbols values are not evaluated.
Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
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notification added.
This change together with use of PhysAddrSpace as the memory
content source for memory and program view allows to access
and monitor contents of peripheral registers and frame-buffer
memory from graphic user interface.
Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
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Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
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Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
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Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
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ProgramTableView::focus_address() calls QAbstractItemView::setCurrentIndex().
verticalScrollBar() value is updated as result of current row change.
This emits signal valueChanged which is connected to ProgramTableView::adjust_scroll_pos().
It checks if the limit of range covered by actual model and row to address offset
is reached. If the top or bottom 1/8 of range is reached then model
needs to be adjusted to cover continuation area. Model shift requires
update of the current row to stay on the same address even that row 0
address offset is changed.
This model shifting is required because range of scroll is only signed
integer and QTableView is even more limited in row count to work
reliably.
Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
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Instructions description in instruction.cpp has been
pragmatically augmented by tool based on Python MIPS simulator,
hazards analyzer
https://github.com/ppisa/apo-simarch
That code has been originally distilled from from GNU
binutils sources.
Implementation is now inline with my original proposal
Previous solution gets untenable with more complex
instructions and its complexity would grow extremely.
MIPS instruction set with coprocessor instructions
which use sel field, rd used as index, rt as destination
and other peculiarities in newer versions cannot
be processed based on basic CPU control signals.
Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
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Instruction parsing is rough and does not support branch offset computation.
Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
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It works like real inserted breakpoint on hardware.
Breakpoint has to be removed to allow code continue
because else instruction is refetch and breakpoint
triggers again. The single step function should
resolve temporal masking of the breakpoint.
Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
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Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
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Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
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