| Commit message (Collapse) | Author | Age | |
|---|---|---|---|
| * | Change single cycle core with delay slot to use separate fetch stage. | Pavel Pisa | 2019-03-26 |
| | | | | | | | | | | | | | When instructions are visualized then it is even more misleading to keep old instruction in decode phase delay buffer. The single cycle core with delay slot is upgraded to the variant with fetch and execute phases. This way the structure is logical and delay slot has purpose. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> | ||
| * | Change instruction views background to match stages color. | Pavel Pisa | 2019-03-26 |
| | | | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> | ||
| * | Use irq 3 (HW1) for Rx and irq 2 (HW0) for Tx to be compatible with SPIM. | Pavel Pisa | 2019-03-04 |
| | | | | | | | | Jump to address 0x8000180 by default and to EBase + 0x180 when EBase is set to be compatible with real MIPS CPU. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> | ||
| * | Implemented interrupt delivery and processing for serial port. | Pavel Pisa | 2019-03-04 |
| | | | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> | ||
| * | Add some more labels and clarify rs, rt, rd in execute stage. | Pavel Pisa | 2019-02-24 |
| | | | | | | | | This allows simple visual compare of rs and rt in execution stage with register number to be written in memory and write-back stages. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> | ||
| * | Adjust label of PC to R31 and add jump to reg. | Pavel Pisa | 2019-02-20 |
| | | | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> | ||
| * | variable font size | Fanda Vacek | 2019-02-19 |
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| * | Report forward and stall for branches and add forward to execution phase. | Pavel Pisa | 2019-02-18 |
| | | | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> | ||
| * | Visualize request to stall and stall in execution phase and exception sources. | Pavel Pisa | 2019-02-18 |
| | | | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> | ||
| * | Include simple serial port terminal and prepare empty peripheral dock. | Pavel Pisa | 2019-02-13 |
| | | | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> | ||
| * | At least partial solution to depict forward paths to compare units/branches. | Pavel Pisa | 2019-02-12 |
| | | | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> | ||
| * | Add signals and multiplexers for ALU inputs forwarding. | Pavel Pisa | 2019-02-12 |
| | | | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> | ||
| * | View register numbers in decimal notation. | Pavel Pisa | 2019-02-07 |
| | | | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> | ||
| * | Add address to emitted instruction to allow its use for branch address decoding. | Pavel Pisa | 2019-02-07 |
| | | | | | | | | | The new Qt5 syntax is used to create connections because old syntax does not work with multiple arguments for some unresolved reason. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> | ||
| * | Add license to the source files. | Pavel Pisa | 2019-02-04 |
| | | | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> | ||
| * | Implement realistic hazard resolution for JR, JALR, BEQ, BNE, BLTZ, BGEZ ↵ | Pavel Pisa | 2019-02-02 |
| | | | | | | | | | | | | instructions. The previous code worked by chance only because decode has been fully processed including forwarding from M and W before PC processing started. But in real hardware the PC processing runs in parallel with ALU and cannot read its results in the same cycle. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> | ||
| * | Initial support for JAL. | Pavel Pisa | 2019-01-31 |
| | | | | | | | | The JR, BEQ, BNE are most probably incorrect still. There is missing forwarding for pipelined execution. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> | ||
| * | Display rs, rt, rd and write register number in all stages. | Pavel Pisa | 2019-01-31 |
| | | | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> | ||
| * | Display execution stage forward signals in the view. | Pavel Pisa | 2019-01-30 |
| | | | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> | ||
| * | Hide some values that shouldn't been visible in no pipelined version | Karel Kočí | 2018-06-20 |
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| * | Fix value position for non-pipelined core | Karel Kočí | 2018-05-24 |
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| * | Add few more labels | Karel Kočí | 2018-05-24 |
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| * | Add few additional labels | Karel Kočí | 2018-05-24 |
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| * | Add buses statis views | Karel Kočí | 2018-05-24 |
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| * | Ignore hazard unit for now | Karel Kočí | 2018-05-23 |
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| * | Drop unneeded parameter from CoreViewScene constructor | Karel Kočí | 2018-04-17 |
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| * | Rename CoreView to GraphicsView | Karel Kočí | 2018-04-15 |
| | | | | | | This generalizes CoreView to be used with other parts of the project too. | ||
| * | Wire up missing control connections | Karel Kočí | 2018-04-14 |
| | | | | | | Now only hazard unit is missing all wires. Anything else is wired up already. | ||
| * | Add control signals for non-pipelined cpu | Karel Kočí | 2018-03-22 |
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| * | Jump to pc address when program counter is double clicked | Karel Kočí | 2018-01-25 |
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| * | Add instruction view to single core | Karel Kočí | 2018-01-21 |
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| * | Update instruction viewers | Karel Kočí | 2018-01-21 |
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| * | Add delay_slot latch for no-pipeline core | Karel Kočí | 2018-01-21 |
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| * | Implement even more parts of the schema | Karel Kočí | 2018-01-21 |
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| * | Implement little bit more of scheme and fix connection angle | Karel Kočí | 2018-01-21 |
| | | | | | | | | | | | This commit adds few more bits to scheme but mainly it chnages how connectors specify angles. Originally it was in radians but we was mapping that trough mathematical operations directly to sizes. But that was problematic because of floating point inacuracy and we sometimes founded intersection where there should be one. So this commit gets rid of this at all and instead allows just some fixes axes to be used instead of arbitrary angles. | ||
| * | More work on coreview | Karel Kočí | 2018-01-18 |
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| * | Add logicblock and Control Unit to scheme | Karel Kočí | 2018-01-17 |
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| * | Add instruction views to core view | Karel Kočí | 2018-01-15 |
| | | | | | Positioning and probably even graphics are just temporally for now. | ||
| * | Add connection between pc adder and multiplexer | Karel Kočí | 2018-01-09 |
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| * | Clean and simplify how we add items to coreview | Karel Kočí | 2018-01-09 |
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| * | Add coreview progress | Karel Kočí | 2018-01-08 |
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| * | Add bounding box and make it grey | Karel Kočí | 2018-01-05 |
| | | | | | | This is just for development purposes. On release this bounding box should be dropped. | ||
| * | Fix how we handle scale of GraphicView | Karel Kočí | 2018-01-05 |
| | | | | | That widget is seriously buggy.. grr | ||
| * | Remove old scene in more appropriate place | Karel Kočí | 2018-01-05 |
| | | | | | | | Previous implementation was pretty confusing. There was no delete on level where variable override was happening. The object removal was implemented inside constructor. Very nasty. | ||
| * | Fix and suppress most of the warnings | Karel Kočí | 2018-01-05 |
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| * | A lot of small changes in gui | Karel Kočí | 2017-12-21 |
| | | | | | | | Added machine status. Widgets now hold size and registers dock has now scrollbars. And more... | ||
| * | Implement alu for coreview | Karel Kočí | 2017-12-17 |
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| * | Put qtmips_machine to machine namespace | Karel Kočí | 2017-12-17 |
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| * | Implement few initial graphic elements | Karel Kočí | 2017-12-15 |
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| * | Another huge pile of work for about two months | Karel Kočí | 2017-11-19 |
| | | | | | | | Well I should commit every change instead of this madness. I am not documenting changes as all this is just improvements and implementation progression. | ||
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