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* Initial attempt to as operating system syscall handler.Pavel Pisa2019-02-13
* Use trick to force knobs to resend signals when machine is newly connected.Pavel Pisa2019-02-13
* Implemented three dials equivalent to MZ_APO RGB dials.Pavel Pisa2019-02-13
* Initialize SP to safe RAM area.Pavel Pisa2019-02-13
* Include simple serial port terminal and prepare empty peripheral dock.Pavel Pisa2019-02-13
* Add simple about dialog and prepare menu entries for serial port and peripher...Pavel Pisa2019-02-13
* Add speed option to run core for time chunks without visualization.Pavel Pisa2019-02-13
* At least partial solution to depict forward paths to compare units/branches.Pavel Pisa2019-02-12
* Add signals and multiplexers for ALU inputs forwarding.Pavel Pisa2019-02-12
* Add ELF library even to the final executables linking to allow build with sta...Pavel Pisa2019-02-12
* Make memory and program listing editable.Pavel Pisa2019-02-12
* Implement LRU as simple priority queue with linear insert sort.Pavel Pisa2019-02-12
* Add debug access to rword and friends to allow read data through cache withou...Pavel Pisa2019-02-12
* Display red background for instruction causing exception and skip HW breakpoi...Pavel Pisa2019-02-11
* Basic "hardware" breakpoints support implemented.Pavel Pisa2019-02-11
* Extend program view to support selected stage followup.Pavel Pisa2019-02-11
* Prepare core for "hardware" breakpoints support and add signals to follow sta...Pavel Pisa2019-02-11
* Converted program listing to be QTableView based.Pavel Pisa2019-02-11
* QTableView based memory view is working.Pavel Pisa2019-02-11
* Implemented workaround QTableView limits workaround which mostly works.Pavel Pisa2019-02-10
* Memory QTableView working for part of the memory range.Pavel Pisa2019-02-10
* Next steps to implement QTableView based memory view.Pavel Pisa2019-02-10
* Correct MemoryDock header fields values.Fanda Vacek2019-02-09
* Initial cleanup of MemoryDock as preparation for switch to QTableView.Pavel Pisa2019-02-09
* Correct build for LLVM.Fanda Vacek2019-02-09
* Minimal implementation of RDHWR to support dummy TLS region.Pavel Pisa2019-02-08
* Move computation of cache row, column and tag to single inline function.Pavel Pisa2019-02-08
* Implement SYNCI as complete cache flush.Pavel Pisa2019-02-08
* Accept SINC and SINCI instructions and flush even instruction cache on CACHE ...Pavel Pisa2019-02-08
* Document InstructionFlags meaning and remove unused IMF_MEM_STORE.Pavel Pisa2019-02-08
* Implement even deprecated BEQL, BNEL, BLEZL, BGTZL, BLTZL, BGEZL, BLTZALL, BG...Pavel Pisa2019-02-08
* Make function to register exception handler accessible from outside.Pavel Pisa2019-02-08
* Implement LL and SC as simple load and store word. SC returns 1 unconditionally.Pavel Pisa2019-02-08
* Add write and read notification to the simple peripheral component.Pavel Pisa2019-02-08
* Exception handlers require even PC of the jump or branch instruction before d...Pavel Pisa2019-02-07
* View register numbers in decimal notation.Pavel Pisa2019-02-07
* Correct cache LocationStatus when cache is disabled.Pavel Pisa2019-02-07
* Implemented simple indication of presence of memory location in the cache.Pavel Pisa2019-02-07
* Added method to retrieve memory location status.Pavel Pisa2019-02-07
* Correct display of jump and branch instructions.Pavel Pisa2019-02-07
* Add address to emitted instruction to allow its use for branch address decoding.Pavel Pisa2019-02-07
* Implemented basic infrastructure to handle exceptions.Pavel Pisa2019-02-07
* Implement BSHFL instruction and ignore RDHWR instruction.Pavel Pisa2019-02-07
* Remove dependency of ALU operation encoding on MIPS instruction format.Pavel Pisa2019-02-07
* Correct BLTZAL and BGEZAL execution to pass unmodified value to R31.Pavel Pisa2019-02-07
* Implemented base for exception handling.Pavel Pisa2019-02-06
* Resolve some memory leaks found by Valgrind.Pavel Pisa2019-02-06
* Provide at least partial cleanup after QtMipsMachine.Pavel Pisa2019-02-06
* Implement simple address-space ranges registration and example peripheral.Pavel Pisa2019-02-06
* Correct registers order in conversion to text for branch instructions.Pavel Pisa2019-02-06
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