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* Implement LUIKarel Kočí2018-04-08
* Implement sync for memoryKarel Kočí2018-04-08
* Ensure that set, block and assoc. is in minimum oneKarel Kočí2018-04-08
* Integrate cache with rest of the machine coreKarel Kočí2018-04-08
* Add associative cacheKarel Kočí2018-04-08
* Tweak shortcuts for primary windowKarel Kočí2018-04-07
* Drop unneeded mask in memory implementationKarel Kočí2018-04-07
* Add initial implementatio of cachesKarel Kočí2018-04-07
* Just note that we are checking endianity automaticallyKarel Kočí2018-04-05
* Use whole words in memoryKarel Kočí2018-04-05
* Add control signals for non-pipelined cpuKarel Kočí2018-03-22
* Append some TODOsKarel Kočí2018-03-06
* Fix forwarding checker for I and J and S* instructionsKarel Kočí2018-03-06
* Implement Cache configurationKarel Kočí2018-03-06
* Forward from execute stage to decode stage latchKarel Kočí2018-02-14
* Do empty fetch stage to report fetch even if we stallKarel Kočí2018-02-14
* Another swap in instruction decodingKarel Kočí2018-02-14
* Swap rs and rt in I instructons decodingKarel Kočí2018-02-14
* Fix signextend in coreKarel Kočí2018-02-14
* Fix program loadingKarel Kočí2018-02-14
* Another fix for memoryview scrollKarel Kočí2018-02-10
* Fix widget docking for MemoryViewKarel Kočí2018-02-05
* Fix focus to take in account number of columnsKarel Kočí2018-01-27
* Add todo for MemoryView with known bugKarel Kočí2018-01-27
* Drop frame from MemoryView completelyKarel Kočí2018-01-27
* Fix some uninitialized jumpsKarel Kočí2018-01-27
* Various graphics tweaksKarel Kočí2018-01-27
* Jump to pc address when program counter is double clickedKarel Kočí2018-01-25
* Implement angle scrollKarel Kočí2018-01-25
* Drop some debug outputsKarel Kočí2018-01-25
* Add focus function to memory viewKarel Kočí2018-01-25
* Fix compilationKarel Kočí2018-01-25
* Implement memoryviewKarel Kočí2018-01-25
* Compile with debug symbols for DEBUG configKarel Kočí2018-01-25
* Better layout registersKarel Kočí2018-01-23
* Hide writeback policy in program cacheKarel Kočí2018-01-23
* Print registers name and don't print dec valueKarel Kočí2018-01-22
* Add instruction view to single coreKarel Kočí2018-01-21
* Update instruction viewersKarel Kočí2018-01-21
* Add delay_slot latch for no-pipeline coreKarel Kočí2018-01-21
* Fix problems with connections rerendeeringKarel Kočí2018-01-21
* Implement even more parts of the schemaKarel Kočí2018-01-21
* Implement little bit more of scheme and fix connection angleKarel Kočí2018-01-21
* More work on coreviewKarel Kočí2018-01-18
* Fix hazard_stall_forward check loadKarel Kočí2018-01-17
* Fix Pipelined core not to accept hazard unit configurationKarel Kočí2018-01-17
* Fix ALU connectors positionsKarel Kočí2018-01-17
* Add logicblock and Control Unit to schemeKarel Kočí2018-01-17
* Fix signal for execute protection config in guiKarel Kočí2018-01-17
* Print I instruction immediate field in hexaKarel Kočí2018-01-17
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