diff options
Diffstat (limited to 'qtmips_machine/tests')
-rw-r--r-- | qtmips_machine/tests/testalu.cpp | 91 | ||||
-rw-r--r-- | qtmips_machine/tests/testcore.cpp | 35 | ||||
-rw-r--r-- | qtmips_machine/tests/testinstruction.cpp | 25 | ||||
-rw-r--r-- | qtmips_machine/tests/testmemory.cpp | 58 | ||||
-rw-r--r-- | qtmips_machine/tests/testprogramloader.cpp | 20 | ||||
-rw-r--r-- | qtmips_machine/tests/tests.pro | 6 | ||||
-rw-r--r-- | qtmips_machine/tests/tst_machine.h | 21 |
7 files changed, 218 insertions, 38 deletions
diff --git a/qtmips_machine/tests/testalu.cpp b/qtmips_machine/tests/testalu.cpp index e69de29..37accdf 100644 --- a/qtmips_machine/tests/testalu.cpp +++ b/qtmips_machine/tests/testalu.cpp @@ -0,0 +1,91 @@ +#include "tst_machine.h" +#include "alu.h" +#include "qtmipsexception.h" + +void MachineTests::alu_data() { + QTest::addColumn<std::uint8_t>("op"); + QTest::addColumn<std::uint32_t>("s"); + QTest::addColumn<std::uint32_t>("t"); + QTest::addColumn<std::uint8_t>("sa"); + QTest::addColumn<std::uint32_t>("res"); + + // TODO SLL-SRAV + QTest::newRow("ADD") << (std::uint8_t)ALU_OP_ADD \ + << (std::uint32_t)24 \ + << (std::uint32_t)66 \ + << (std::uint8_t)0 \ + << (std::uint32_t)90; + QTest::newRow("ADDU") << (std::uint8_t)ALU_OP_ADDU \ + << (std::uint32_t)24 \ + << (std::uint32_t)66 \ + << (std::uint8_t)0 \ + << (std::uint32_t)90; + QTest::newRow("SUB") << (std::uint8_t)ALU_OP_SUB \ + << (std::uint32_t)66 \ + << (std::uint32_t)24 \ + << (std::uint8_t)0 \ + << (std::uint32_t)42; + QTest::newRow("SUBU") << (std::uint8_t)ALU_OP_SUBU \ + << (std::uint32_t)24 \ + << (std::uint32_t)66 \ + << (std::uint8_t)0 \ + << (std::uint32_t)-42; + QTest::newRow("AND") << (std::uint8_t)ALU_OP_AND \ + << (std::uint32_t)0xA81 \ + << (std::uint32_t)0x603 \ + << (std::uint8_t)0 \ + << (std::uint32_t)0x201; + QTest::newRow("OR") << (std::uint8_t)ALU_OP_OR \ + << (std::uint32_t)0xA81 \ + << (std::uint32_t)0x603 \ + << (std::uint8_t)0 \ + << (std::uint32_t)0xE83; + QTest::newRow("XOR") << (std::uint8_t)ALU_OP_XOR \ + << (std::uint32_t)0xA81 \ + << (std::uint32_t)0x603 \ + << (std::uint8_t)0 \ + << (std::uint32_t)0xC82; + QTest::newRow("NOR") << (std::uint8_t)ALU_OP_NOR \ + << (std::uint32_t)0xA81 \ + << (std::uint32_t)0x603 \ + << (std::uint8_t)0 \ + << (std::uint32_t)0xFFFFF17C; + // TODO SLT-SLTU +} + +void MachineTests::alu() { + QFETCH(std::uint8_t, op); + QFETCH(std::uint32_t, s); + QFETCH(std::uint32_t, t); + QFETCH(std::uint8_t, sa); + QFETCH(std::uint32_t, res); + + QCOMPARE(alu_operate((enum AluOp)op, s , t, sa), res); +} + +void MachineTests::alu_except_data() { + QTest::addColumn<std::uint8_t>("op"); + QTest::addColumn<std::uint32_t>("s"); + QTest::addColumn<std::uint32_t>("t"); + // Note no sa as shift unstruction has no exceptions + + QTest::newRow("ADD") << (std::uint8_t)ALU_OP_ADD \ + << (std::uint32_t)0x8fffffff \ + << (std::uint32_t)0x90000000; + QTest::newRow("SUB") << (std::uint8_t)ALU_OP_SUB \ + << (std::uint32_t)3 \ + << (std::uint32_t)4; + // Just test that we can throw unsupported ALU operation + QTest::newRow("?") << (std::uint8_t)ALU_OP_LAST \ + << (std::uint32_t)0 \ + << (std::uint32_t)0; +} + +void MachineTests::alu_except() { + QFETCH(std::uint8_t, op); + QFETCH(std::uint32_t, s); + QFETCH(std::uint32_t, t); + + // Only runtime exception is expected as any other exception is a bug + QVERIFY_EXCEPTION_THROWN(alu_operate((enum AluOp)op, s , t, 0), QtMipsExceptionRuntime); +} diff --git a/qtmips_machine/tests/testcore.cpp b/qtmips_machine/tests/testcore.cpp index e69de29..bbf8086 100644 --- a/qtmips_machine/tests/testcore.cpp +++ b/qtmips_machine/tests/testcore.cpp @@ -0,0 +1,35 @@ +#include "tst_machine.h" +#include "core.h" + +void MachineTests::core_regs_data() { + /* + QTest::addColumn<Instruction>("i"); + QTest::addColumn<Registers>("init"); + QTest::addColumn<Registers>("res"); + + // Test arithmetic instructions + { + Registers regs_init(); + regs_init.write_gp(24, 12); + regs_init.write_gp(25, 24); + Registers regs_res(®s_init); + regs_res.write_gp(26, 36); + QTest::newRow("ADD") << Instruction(0, 24, 25, 26, 0, 32) \ + << regs_init \ + << regs_res; + } + */ + // TODO test other operations +} + +void MachineTests::core_regs() { + +} + +void MachineTests::core_mem_data() { + +} + +void MachineTests::core_mem() { + +} diff --git a/qtmips_machine/tests/testinstruction.cpp b/qtmips_machine/tests/testinstruction.cpp index e69de29..4efedac 100644 --- a/qtmips_machine/tests/testinstruction.cpp +++ b/qtmips_machine/tests/testinstruction.cpp @@ -0,0 +1,25 @@ +#include "tst_machine.h" +#include "instruction.h" + +// Test that we are correctly encoding instructions in constructor +void MachineTests::instruction() { + QCOMPARE(Instruction(0x00), Instruction(0,0)); + QCOMPARE(Instruction(0x4000002), Instruction(1, 2)); + // QCOMPARE(Instruction(0x4000002), Instruction(1, 2, 3, 4)); + // TODO other combinations +} + +// Test that we are correctly decoding instruction fields +void MachineTests::instruction_access() { + Instruction i(0xffffffff); + + QCOMPARE(i.data(), (std::uint32_t) 0xffffffff); + QCOMPARE(i.opcode(), (std::uint8_t) 0x3f); + QCOMPARE(i.rs(), (std::uint8_t) 0x1f); + QCOMPARE(i.rt(), (std::uint8_t) 0x1f); + QCOMPARE(i.rd(), (std::uint8_t) 0x1f); + QCOMPARE(i.shamt(), (std::uint8_t) 0x1f); + QCOMPARE(i.funct(), (std::uint8_t) 0x3f); + QCOMPARE(i.immediate(), (std::uint16_t) 0xffff); + QCOMPARE(i.address(), (std::uint32_t) 0x3ffffff); +} diff --git a/qtmips_machine/tests/testmemory.cpp b/qtmips_machine/tests/testmemory.cpp index eac7dd6..e450231 100644 --- a/qtmips_machine/tests/testmemory.cpp +++ b/qtmips_machine/tests/testmemory.cpp @@ -13,21 +13,21 @@ void MachineTests::memory_data() { void MachineTests::memory() { Memory m; - QFETCH(std::uint32_t, address); + QFETCH(std::uint32_t, address); - // Uninitialize memory should read as zero - QCOMPARE(m.read_byte(address), (std::uint8_t)0); - QCOMPARE(m.read_hword(address), (std::uint16_t)0); - QCOMPARE(m.read_word(address), (std::uint32_t)0); - // Just a byte - m.write_byte(address, 0x42); - QCOMPARE(m.read_byte(address), (std::uint8_t)0x42); - // Half word - m.write_hword(address, 0x4243); - QCOMPARE(m.read_hword(address), (std::uint16_t)0x4243); - // Word - m.write_word(address, 0x42434445); - QCOMPARE(m.read_word(address), (std::uint32_t)0x42434445); + // Uninitialize memory should read as zero + QCOMPARE(m.read_byte(address), (std::uint8_t)0); + QCOMPARE(m.read_hword(address), (std::uint16_t)0); + QCOMPARE(m.read_word(address), (std::uint32_t)0); + // Just a byte + m.write_byte(address, 0x42); + QCOMPARE(m.read_byte(address), (std::uint8_t)0x42); + // Half word + m.write_hword(address, 0x4243); + QCOMPARE(m.read_hword(address), (std::uint16_t)0x4243); + // Word + m.write_word(address, 0x42434445); + QCOMPARE(m.read_word(address), (std::uint32_t)0x42434445); } void MachineTests::memory_section_data() { @@ -40,24 +40,24 @@ void MachineTests::memory_section_data() { } void MachineTests::memory_section() { - Memory m; + Memory m; - QFETCH(std::uint32_t, address); + QFETCH(std::uint32_t, address); - // First section shouldn't exists - QCOMPARE(m.get_section(address, false), (MemorySection*)nullptr); - // Create section - MemorySection *s = m.get_section(address, true); - QVERIFY(s != nullptr); + // First section shouldn't exists + QCOMPARE(m.get_section(address, false), (MemorySection*)nullptr); + // Create section + MemorySection *s = m.get_section(address, true); + QVERIFY(s != nullptr); - // Write some data to memory - m.write_byte(address, 0x42); - // Read it trough section (mask bits outside of the memory section) - QCOMPARE(s->read_byte(address & ((1 << MEMORY_SECTION_BITS) - 1)), (std::uint8_t)0x42); - // Write some other data trough section - s->write_byte(address & ((1 << MEMORY_SECTION_BITS) - 1), 0x66); - // Read trough memory - QCOMPARE(m.read_byte(address), (std::uint8_t)0x66); + // Write some data to memory + m.write_byte(address, 0x42); + // Read it trough section (mask bits outside of the memory section) + QCOMPARE(s->read_byte(address & ((1 << MEMORY_SECTION_BITS) - 1)), (std::uint8_t)0x42); + // Write some other data trough section + s->write_byte(address & ((1 << MEMORY_SECTION_BITS) - 1), 0x66); + // Read trough memory + QCOMPARE(m.read_byte(address), (std::uint8_t)0x66); } void MachineTests::memory_endian() { diff --git a/qtmips_machine/tests/testprogramloader.cpp b/qtmips_machine/tests/testprogramloader.cpp index e69de29..7ff1c54 100644 --- a/qtmips_machine/tests/testprogramloader.cpp +++ b/qtmips_machine/tests/testprogramloader.cpp @@ -0,0 +1,20 @@ +#include <iostream> +#include "tst_machine.h" +#include "programloader.h" +#include "instruction.h" + +// This is common program start (initial value of program counter) +#define PC_INIT 0x80020000 + +void MachineTests::program_loader() { + ProgramLoader pl("data"); + Memory m; + pl.to_memory(&m); + + // addi $1, $0, 6 + QCOMPARE(Instruction(m.read_word(PC_INIT)), Instruction(8, 0, 1, 6)); + // j 80020000 + // TODO wtf to je relativni skok asi tady + //QCOMPARE(Instruction(m.read_word(PC_INIT + 4)), Instruction(2, PC_INIT)); + // TODO add some more code to data and do more compares (for example more sections) +} diff --git a/qtmips_machine/tests/tests.pro b/qtmips_machine/tests/tests.pro index 287d1e8..ffe75b7 100644 --- a/qtmips_machine/tests/tests.pro +++ b/qtmips_machine/tests/tests.pro @@ -18,8 +18,10 @@ DEFINES += QT_DEPRECATED_WARNINGS SOURCES += tst_machine.cpp \ testmemory.cpp \ testregisters.cpp \ - testprogrammemory.cpp \ - testinstruction.cpp + testprogramloader.cpp \ + testinstruction.cpp \ + testalu.cpp \ + testcore.cpp HEADERS += tst_machine.h diff --git a/qtmips_machine/tests/tst_machine.h b/qtmips_machine/tests/tst_machine.h index c05e8ad..da8082a 100644 --- a/qtmips_machine/tests/tst_machine.h +++ b/qtmips_machine/tests/tst_machine.h @@ -17,14 +17,21 @@ private Q_SLOTS: void memory_section(); void memory_section_data(); void memory_endian(); - // ProgramMemory - void program_memory(); - void program_memory_data(); + // Program loader + void program_loader(); // Instruction - void instruction_arithmetic(); - void instruction_arithmetic_data(); - void instruction_arithmetic_immediate(); - void instruction_arithmetic_immediate_data(); + void instruction(); + void instruction_access(); + // Alu + void alu(); + void alu_data(); + void alu_except(); + void alu_except_data(); + // Core + void core_regs(); + void core_regs_data(); + void core_mem(); + void core_mem_data(); }; #endif // TST_MACHINE_H |