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author | Karel Kočí <cynerd@email.cz> | 2018-01-03 17:52:45 +0100 |
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committer | Karel Kočí <cynerd@email.cz> | 2018-01-03 17:52:45 +0100 |
commit | 08d7e3dabd81e9d6e4f73aa5889a1d709242177c (patch) | |
tree | 1ad8277b3be1534f3d2a451e6c4fe659f9d9cb24 /qtmips_machine/tests | |
parent | 4a40dddda4d3839814be2f00fb9a62f95b1b3f21 (diff) | |
download | qtmips-08d7e3dabd81e9d6e4f73aa5889a1d709242177c.tar.gz qtmips-08d7e3dabd81e9d6e4f73aa5889a1d709242177c.tar.bz2 qtmips-08d7e3dabd81e9d6e4f73aa5889a1d709242177c.zip |
Allow delay slot disable for non-pipelined core
Diffstat (limited to 'qtmips_machine/tests')
-rw-r--r-- | qtmips_machine/tests/testcore.cpp | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/qtmips_machine/tests/testcore.cpp b/qtmips_machine/tests/testcore.cpp index 0bd18ba..1e5b502 100644 --- a/qtmips_machine/tests/testcore.cpp +++ b/qtmips_machine/tests/testcore.cpp @@ -186,7 +186,7 @@ void MachineTests::singlecore_regs() { mem.write_word(res.read_pc(), i.data()); // Store single instruction (anything else should be 0 so NOP effectively) Memory mem_used(mem); // Create memory copy - CoreSingle core(&init, &mem_used); + CoreSingle core(&init, &mem_used, true); core.step(); // Single step should be enought as this is risc without pipeline res.pc_inc(); // We did single step so increment program counter accordingly @@ -272,7 +272,7 @@ void MachineTests::singlecore_jmp() { Memory mem_used(mem); Registers regs_used(regs); - CoreSingle core(®s_used, &mem_used); + CoreSingle core(®s_used, &mem_used, true); core.step(); QCOMPARE(regs.read_pc() + 4, regs_used.read_pc()); // First execute delay slot core.step(); @@ -397,7 +397,7 @@ void MachineTests::singlecore_mem() { mem_init.write_word(regs_init.read_pc(), i.data()); mem_res.write_word(regs_init.read_pc(), i.data()); - CoreSingle core(®s_init, &mem_init); + CoreSingle core(®s_init, &mem_init, true); core.step(); regs_res.pc_inc(); |