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authorKarel Kočí <cynerd@email.cz>2017-12-12 18:53:02 +0100
committerKarel Kočí <cynerd@email.cz>2017-12-12 18:53:02 +0100
commit15398c34d38489bf14a100bbf01fb9fb4c7e46cb (patch)
tree7121325d9ba6d1166b7faa4b8664bdcac875d995 /qtmips_machine/core.h
parent36853877b262bd47417be1637a1854ae3145384e (diff)
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Implement branch and jump instructions
Diffstat (limited to 'qtmips_machine/core.h')
-rw-r--r--qtmips_machine/core.h10
1 files changed, 9 insertions, 1 deletions
diff --git a/qtmips_machine/core.h b/qtmips_machine/core.h
index b566a38..6366088 100644
--- a/qtmips_machine/core.h
+++ b/qtmips_machine/core.h
@@ -31,7 +31,6 @@ protected:
bool alusrc; // If second value to alu is immediate value (rt used otherwise)
bool regd; // If rd is used (otherwise rt is used for write target)
bool regwrite; // If output should be written back to register (which one depends on regd)
- bool branch; // If this is branch instruction
enum AluOp aluop; // Decoded ALU operation
std::uint32_t val_rs; // Value from register rs
std::uint32_t val_rt; // Value from register rt
@@ -54,7 +53,13 @@ protected:
struct dtExecute execute(struct dtDecode);
struct dtMemory memory(struct dtExecute);
void writeback(struct dtMemory);
+ void handle_pc(struct dtDecode);
+ // Initialize structures to NOPE instruction
+ void dtFetchInit(struct dtFetch &dt);
+ void dtDecodeInit(struct dtDecode &dt);
+ void dtExecuteInit(struct dtExecute &dt);
+ void dtMemoryInit(struct dtMemory &dt);
};
class CoreSingle : public Core {
@@ -62,6 +67,9 @@ public:
CoreSingle(Registers *regs, MemoryAccess *mem);
void step();
+
+private:
+ struct Core::dtDecode jmp_delay_decode;
};
class CorePipelined : public Core {