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| author | Karel Kočí <cynerd@email.cz> | 2017-11-21 22:37:59 +0100 |
|---|---|---|
| committer | Karel Kočí <cynerd@email.cz> | 2017-11-21 22:37:59 +0100 |
| commit | c4efaa81d4bf498c721db5cdbf932e7a3bcb0cae (patch) | |
| tree | adffb9dfb4b0d020aa68484bca961c8f3083e5f7 /instructions.md | |
| parent | cd9e572b6523fac483ce1695ae1785fca075cc53 (diff) | |
| download | qtmips-c4efaa81d4bf498c721db5cdbf932e7a3bcb0cae.tar.gz qtmips-c4efaa81d4bf498c721db5cdbf932e7a3bcb0cae.tar.bz2 qtmips-c4efaa81d4bf498c721db5cdbf932e7a3bcb0cae.zip | |
Implement tests for few more arithmetic instructions
Diffstat (limited to 'instructions.md')
| -rw-r--r-- | instructions.md | 27 |
1 files changed, 14 insertions, 13 deletions
diff --git a/instructions.md b/instructions.md index bbeac20..a3ee0a0 100644 --- a/instructions.md +++ b/instructions.md @@ -4,6 +4,7 @@ This is list of all MIPS1 instructions and their implementation status in QtMips Explanation of checkboxes: * [ ] Not tested +* [?] Somewhat tested but not sure about correctness of implementation * [-] Tested non-pipelined core * [x] Tested on non-pipelined and pipelined core @@ -12,7 +13,7 @@ CPU Arithmetic Instruction * [-] ADD * [ ] ADDI * [ ] ADDIU -* [ ] ADDU +* [-] ADDU * [ ] CLO * [ ] CLZ * [ ] DIV @@ -24,12 +25,12 @@ CPU Arithmetic Instruction * [ ] MUL * [ ] MULT * [ ] MULTU -* [ ] SLT +* [-] SLT * [ ] SLTI * [ ] SLTIU -* [ ] SLTU -* [ ] SUB -* [ ] SUBU +* [?] SLTU +* [-] SUB +* [-] SUBU CPU Branch and Jump Instructions -------------------------------- @@ -48,8 +49,8 @@ CPU Branch and Jump Instructions * [ ] JALR * [ ] JR -CPU Instruction Control Instruction ------------------------------------ +CPU No Instructions +------------------- * [ ] NOP * [ ] SSNOP @@ -96,12 +97,12 @@ CPU Move Instruction CPU Shift Instructions ---------------------- -* [ ] SLL -* [ ] SLLV -* [ ] SRA -* [ ] SRAV -* [ ] SRL -* [ ] SRLV +* [-] SLL +* [-] SLLV +* [?] SRA +* [?] SRAV +* [-] SRL +* [-] SRLV CPU Trap Instructions --------------------- |