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authorPavel Pisa <pisa@cmp.felk.cvut.cz>2019-02-18 14:50:52 +0100
committerPavel Pisa <pisa@cmp.felk.cvut.cz>2019-02-18 14:50:52 +0100
commit40ec86b16e297030f8fca02022dfa7a3e418b719 (patch)
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parent22475cd499be28d86eee2d87a3dabd425cb0b69c (diff)
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Stall the pipeline even for branch which requires memory read as argument.
This type of the hazard doe not cause problems in the simulator because processing of memory stage is already finished at time when PC handling is started but it would cause problems in real hardware where PC handling is processed in parallel to memory load. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
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