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| author | Karel Kočí <cynerd@email.cz> | 2017-11-21 23:54:04 +0100 |
|---|---|---|
| committer | Karel Kočí <cynerd@email.cz> | 2017-11-21 23:54:04 +0100 |
| commit | f5d4468b2a8afa28ddad0bad425f762725eb69a7 (patch) | |
| tree | 618b54866130da61a65968775a5550960e8c954c | |
| parent | 054225612d13e9a32b7900e423590367b5969b6e (diff) | |
| download | qtmips-f5d4468b2a8afa28ddad0bad425f762725eb69a7.tar.gz qtmips-f5d4468b2a8afa28ddad0bad425f762725eb69a7.tar.bz2 qtmips-f5d4468b2a8afa28ddad0bad425f762725eb69a7.zip | |
Implement some logical operations
| -rw-r--r-- | instructions.md | 14 | ||||
| -rw-r--r-- | qtmips_machine/core.cpp | 16 | ||||
| -rw-r--r-- | qtmips_machine/tests/testcore.cpp | 34 |
3 files changed, 49 insertions, 15 deletions
diff --git a/instructions.md b/instructions.md index 81a0d76..11ea04e 100644 --- a/instructions.md +++ b/instructions.md @@ -76,14 +76,14 @@ CPU Load, Store and Memory Control Instructions CPU Logical Instructions ------------------------ -* [ ] AND -* [ ] ANDI +* [-] AND +* [-] ANDI * [ ] LUI -* [ ] NOR -* [ ] OR -* [ ] ORI -* [ ] XOR -* [ ] XORI +* [-] NOR +* [-] OR +* [-] ORI +* [-] XOR +* [-] XORI CPU Move Instruction -------------------- diff --git a/qtmips_machine/core.cpp b/qtmips_machine/core.cpp index c79801c..d86a6f4 100644 --- a/qtmips_machine/core.cpp +++ b/qtmips_machine/core.cpp @@ -18,6 +18,8 @@ // This is temporally operation place holder #define NOPE { .flags = 0, .alu = ALU_OP_SLL } +#define FLAGS_ALU_I (DM_SUPPORTED | DM_ALUSRC | DM_REGWRITE) + // This is map from opcode to signals. static const struct DecodeMap dmap[] = { { .flags = DM_SUPPORTED | DM_REGD | DM_REGWRITE, .alu = ALU_OP_SLL }, // Alu operations @@ -28,13 +30,13 @@ static const struct DecodeMap dmap[] = { NOPE, // BNE NOPE, // BLEZ NOPE, // BGTZ - { .flags = DM_SUPPORTED | DM_ALUSRC | DM_REGWRITE, .alu = ALU_OP_ADD }, // ADDI - { .flags = DM_SUPPORTED | DM_ALUSRC | DM_REGWRITE, .alu = ALU_OP_ADDU }, // ADDIU - { .flags = DM_SUPPORTED | DM_ALUSRC | DM_REGWRITE, .alu = ALU_OP_SLT }, // SLTI - { .flags = DM_SUPPORTED | DM_ALUSRC | DM_REGWRITE, .alu = ALU_OP_SLTU }, // SLTIU - NOPE, // ANDI - NOPE, // ORI - NOPE, // XORI + { .flags = FLAGS_ALU_I, .alu = ALU_OP_ADD }, // ADDI + { .flags = FLAGS_ALU_I, .alu = ALU_OP_ADDU }, // ADDIU + { .flags = FLAGS_ALU_I, .alu = ALU_OP_SLT }, // SLTI + { .flags = FLAGS_ALU_I, .alu = ALU_OP_SLTU }, // SLTIU + { .flags = FLAGS_ALU_I, .alu = ALU_OP_AND }, // ANDI + { .flags = FLAGS_ALU_I, .alu = ALU_OP_OR }, // ORI + { .flags = FLAGS_ALU_I, .alu = ALU_OP_XOR }, // XORI NOPE, // LUI NOPE, // 16 NOPE, // 17 diff --git a/qtmips_machine/tests/testcore.cpp b/qtmips_machine/tests/testcore.cpp index 3a48f1d..43d4c90 100644 --- a/qtmips_machine/tests/testcore.cpp +++ b/qtmips_machine/tests/testcore.cpp @@ -88,7 +88,39 @@ void MachineTests::core_regs_data() { << regs_init \ << regs_res; } - // TODO test other operations + + // Logical instructions + { + Registers regs_init; + regs_init.write_gp(24, 0xf0); + regs_init.write_gp(25, 0xe1); + Registers regs_res(regs_init); + regs_res.write_gp(26, 0xe0); + QTest::newRow("AND") << Instruction(0, 24, 25, 26, 0, 36) \ + << regs_init \ + << regs_res; + QTest::newRow("ANDI") << Instruction(12, 24, 26, 0xe1) \ + << regs_init \ + << regs_res; + regs_res.write_gp(26, 0xf1); + QTest::newRow("OR") << Instruction(0, 24, 25, 26, 0, 37) \ + << regs_init \ + << regs_res; + QTest::newRow("ORI") << Instruction(13, 24, 26, 0xe1) \ + << regs_init \ + << regs_res; + regs_res.write_gp(26, 0x11); + QTest::newRow("XOR") << Instruction(0, 24, 25, 26, 0, 38) \ + << regs_init \ + << regs_res; + QTest::newRow("XORI") << Instruction(14, 24, 26, 0xe1) \ + << regs_init \ + << regs_res; + regs_res.write_gp(26, 0xffffff0e); + QTest::newRow("NOR") << Instruction(0, 24, 25, 26, 0, 39) \ + << regs_init \ + << regs_res; + } } #include <iostream> |