From 462a088c474832b19ff2730de1e6bea66d399c23 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Karel=20Ko=C4=8D=C3=AD?= Date: Sat, 15 Oct 2022 23:01:29 +0200 Subject: Add Turris kernel (includes patches from OpenWrt) --- ...-net-phylink-tidy-up-disable-bit-clearing.patch | 70 ++++++++++++++++++++++ 1 file changed, 70 insertions(+) create mode 100644 pkgs/patches-linux-5.15/782-v5.17-1-net-phylink-tidy-up-disable-bit-clearing.patch (limited to 'pkgs/patches-linux-5.15/782-v5.17-1-net-phylink-tidy-up-disable-bit-clearing.patch') diff --git a/pkgs/patches-linux-5.15/782-v5.17-1-net-phylink-tidy-up-disable-bit-clearing.patch b/pkgs/patches-linux-5.15/782-v5.17-1-net-phylink-tidy-up-disable-bit-clearing.patch new file mode 100644 index 0000000..07fbe0f --- /dev/null +++ b/pkgs/patches-linux-5.15/782-v5.17-1-net-phylink-tidy-up-disable-bit-clearing.patch @@ -0,0 +1,70 @@ +From 219b507f5c0a08507c17ecf4df80eaa1ccb0f3b7 Mon Sep 17 00:00:00 2001 +From: Russell King +Date: Tue, 30 Nov 2021 14:49:41 +0000 +Subject: [PATCH 1/2] net: phylink: tidy up disable bit clearing +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Tidy up the disable bit clearing where we clear a bit +and then run the link resolver. + +Signed-off-by: Russell King +Reviewed-by: Marek Behún +Reviewed-by: Andrew Lunn +Link: https://lore.kernel.org/r/E1ms4Rx-00EKEc-En@rmk-PC.armlinux.org.uk +Signed-off-by: Jakub Kicinski +--- + drivers/net/phy/phylink.c | 15 +++++++++------ + 1 file changed, 9 insertions(+), 6 deletions(-) + +diff --git a/drivers/net/phy/phylink.c b/drivers/net/phy/phylink.c +index 3e1d7dea616d..e95c6086d811 100644 +--- a/drivers/net/phy/phylink.c ++++ b/drivers/net/phy/phylink.c +@@ -1149,6 +1149,12 @@ static void phylink_run_resolve_and_disable(struct phylink *pl, int bit) + } + } + ++static void phylink_enable_and_run_resolve(struct phylink *pl, int bit) ++{ ++ clear_bit(bit, &pl->phylink_disable_state); ++ phylink_run_resolve(pl); ++} ++ + static void phylink_fixed_poll(struct timer_list *t) + { + struct phylink *pl = container_of(t, struct phylink, link_poll); +@@ -1636,8 +1642,7 @@ void phylink_start(struct phylink *pl) + */ + phylink_mac_initial_config(pl, true); + +- clear_bit(PHYLINK_DISABLE_STOPPED, &pl->phylink_disable_state); +- phylink_run_resolve(pl); ++ phylink_enable_and_run_resolve(pl, PHYLINK_DISABLE_STOPPED); + + if (pl->cfg_link_an_mode == MLO_AN_FIXED && pl->link_gpio) { + int irq = gpiod_to_irq(pl->link_gpio); +@@ -1777,8 +1782,7 @@ void phylink_resume(struct phylink *pl) + phylink_mac_initial_config(pl, true); + + /* Re-enable and re-resolve the link parameters */ +- clear_bit(PHYLINK_DISABLE_MAC_WOL, &pl->phylink_disable_state); +- phylink_run_resolve(pl); ++ phylink_enable_and_run_resolve(pl, PHYLINK_DISABLE_MAC_WOL); + } else { + phylink_start(pl); + } +@@ -2817,8 +2821,7 @@ static void phylink_sfp_link_up(void *upstream) + + ASSERT_RTNL(); + +- clear_bit(PHYLINK_DISABLE_LINK, &pl->phylink_disable_state); +- phylink_run_resolve(pl); ++ phylink_enable_and_run_resolve(pl, PHYLINK_DISABLE_LINK); + } + + /* The Broadcom BCM84881 in the Methode DM7052 is unable to provide a SGMII +-- +2.35.1 + -- cgit v1.2.3