From 462a088c474832b19ff2730de1e6bea66d399c23 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Karel=20Ko=C4=8D=C3=AD?= Date: Sat, 15 Oct 2022 23:01:29 +0200 Subject: Add Turris kernel (includes patches from OpenWrt) --- ...e-Fix-assigned-addresses-for-every-PCIe-R.patch | 35 ++++++++++++++++++++++ 1 file changed, 35 insertions(+) create mode 100644 pkgs/patches-linux-5.15/0057-ARM-dts-dove-Fix-assigned-addresses-for-every-PCIe-R.patch (limited to 'pkgs/patches-linux-5.15/0057-ARM-dts-dove-Fix-assigned-addresses-for-every-PCIe-R.patch') diff --git a/pkgs/patches-linux-5.15/0057-ARM-dts-dove-Fix-assigned-addresses-for-every-PCIe-R.patch b/pkgs/patches-linux-5.15/0057-ARM-dts-dove-Fix-assigned-addresses-for-every-PCIe-R.patch new file mode 100644 index 0000000..99f1872 --- /dev/null +++ b/pkgs/patches-linux-5.15/0057-ARM-dts-dove-Fix-assigned-addresses-for-every-PCIe-R.patch @@ -0,0 +1,35 @@ +From ebcb5a3c9803cacf33ff2d029325519a4e27ec66 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Pali=20Roh=C3=A1r?= +Date: Wed, 17 Aug 2022 23:46:32 +0200 +Subject: [PATCH 57/90] ARM: dts: dove: Fix assigned-addresses for every PCIe + Root Port +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +BDF of resource in DT assigned-addresses property of Marvell PCIe Root Port +(PCI-to-PCI bridge) should match BDF in address part in that DT node name +as specified resource belongs to Marvell PCIe Root Port itself. + +Fixes: 74ecaa403a74 ("ARM: dove: add PCIe controllers to SoC DT") +Signed-off-by: Pali Rohár +--- + arch/arm/boot/dts/dove.dtsi | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/arm/boot/dts/dove.dtsi b/arch/arm/boot/dts/dove.dtsi +index 96ba47c061a7..70d45d2b1258 100644 +--- a/arch/arm/boot/dts/dove.dtsi ++++ b/arch/arm/boot/dts/dove.dtsi +@@ -139,7 +139,7 @@ pcie0_intc: interrupt-controller { + pcie1: pcie@2 { + device_type = "pci"; + status = "disabled"; +- assigned-addresses = <0x82002800 0 0x80000 0 0x2000>; ++ assigned-addresses = <0x82001000 0 0x80000 0 0x2000>; + reg = <0x1000 0 0 0 0>; + clocks = <&gate_clk 5>; + marvell,pcie-port = <1>; +-- +2.34.1 + -- cgit v1.2.3