From 462a088c474832b19ff2730de1e6bea66d399c23 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Karel=20Ko=C4=8D=C3=AD?= Date: Sat, 15 Oct 2022 23:01:29 +0200 Subject: Add Turris kernel (includes patches from OpenWrt) --- ...pdate-comment-for-PCI_EXP_LNKCTL-register.patch | 39 ++++++++++++++++++++++ 1 file changed, 39 insertions(+) create mode 100644 pkgs/patches-linux-5.15/0022-PCI-mvebu-Update-comment-for-PCI_EXP_LNKCTL-register.patch (limited to 'pkgs/patches-linux-5.15/0022-PCI-mvebu-Update-comment-for-PCI_EXP_LNKCTL-register.patch') diff --git a/pkgs/patches-linux-5.15/0022-PCI-mvebu-Update-comment-for-PCI_EXP_LNKCTL-register.patch b/pkgs/patches-linux-5.15/0022-PCI-mvebu-Update-comment-for-PCI_EXP_LNKCTL-register.patch new file mode 100644 index 0000000..49bd9e2 --- /dev/null +++ b/pkgs/patches-linux-5.15/0022-PCI-mvebu-Update-comment-for-PCI_EXP_LNKCTL-register.patch @@ -0,0 +1,39 @@ +From b47763b59b70859fdcb98e228ac5d762cca39ab7 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Pali=20Roh=C3=A1r?= +Date: Fri, 17 Sep 2021 11:57:20 +0200 +Subject: [PATCH 22/90] PCI: mvebu: Update comment for PCI_EXP_LNKCTL register + on emulated bridge +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Logic and code for clearing PCI_EXP_LNKCTL_CLKREQ_EN bit is correct, but +comment describing it is misleading. PCI_EXP_LNKCTL_CLKREQ_EN bit should be +hardwired to zero but mvebu hw allows to change it. + +Signed-off-by: Pali Rohár +--- + drivers/pci/controller/pci-mvebu.c | 7 +++---- + 1 file changed, 3 insertions(+), 4 deletions(-) + +diff --git a/drivers/pci/controller/pci-mvebu.c b/drivers/pci/controller/pci-mvebu.c +index 1aac65977b97..dffa330de174 100644 +--- a/drivers/pci/controller/pci-mvebu.c ++++ b/drivers/pci/controller/pci-mvebu.c +@@ -663,10 +663,9 @@ mvebu_pci_bridge_emul_pcie_conf_write(struct pci_bridge_emul *bridge, + + case PCI_EXP_LNKCTL: + /* +- * If we don't support CLKREQ, we must ensure that the +- * CLKREQ enable bit always reads zero. Since we haven't +- * had this capability, and it's dependent on board wiring, +- * disable it for the time being. ++ * PCIe requires that the Enable Clock Power Management bit ++ * is hard-wired to zero for downstream ports but HW allows ++ * to change it. + */ + new &= ~PCI_EXP_LNKCTL_CLKREQ_EN; + +-- +2.34.1 + -- cgit v1.2.3