From 462a088c474832b19ff2730de1e6bea66d399c23 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Karel=20Ko=C4=8D=C3=AD?= Date: Sat, 15 Oct 2022 23:01:29 +0200 Subject: Add Turris kernel (includes patches from OpenWrt) --- ...pdate-comment-for-PCI_EXP_LNKCAP-register.patch | 34 ++++++++++++++++++++++ 1 file changed, 34 insertions(+) create mode 100644 pkgs/patches-linux-5.15/0021-PCI-mvebu-Update-comment-for-PCI_EXP_LNKCAP-register.patch (limited to 'pkgs/patches-linux-5.15/0021-PCI-mvebu-Update-comment-for-PCI_EXP_LNKCAP-register.patch') diff --git a/pkgs/patches-linux-5.15/0021-PCI-mvebu-Update-comment-for-PCI_EXP_LNKCAP-register.patch b/pkgs/patches-linux-5.15/0021-PCI-mvebu-Update-comment-for-PCI_EXP_LNKCAP-register.patch new file mode 100644 index 0000000..1239337 --- /dev/null +++ b/pkgs/patches-linux-5.15/0021-PCI-mvebu-Update-comment-for-PCI_EXP_LNKCAP-register.patch @@ -0,0 +1,34 @@ +From 91948e605b7b0f3f65919d6e19ef4e39535faf6a Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Pali=20Roh=C3=A1r?= +Date: Fri, 17 Sep 2021 11:54:37 +0200 +Subject: [PATCH 21/90] PCI: mvebu: Update comment for PCI_EXP_LNKCAP register + on emulated bridge +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Reason for clearing this bit is because mvebu hw returns incorrectly this bit set to 1. + +Signed-off-by: Pali Rohár +--- + drivers/pci/controller/pci-mvebu.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/drivers/pci/controller/pci-mvebu.c b/drivers/pci/controller/pci-mvebu.c +index 94ef00b6d697..1aac65977b97 100644 +--- a/drivers/pci/controller/pci-mvebu.c ++++ b/drivers/pci/controller/pci-mvebu.c +@@ -546,8 +546,8 @@ mvebu_pci_bridge_emul_pcie_conf_read(struct pci_bridge_emul *bridge, + + case PCI_EXP_LNKCAP: + /* +- * PCIe requires the clock power management capability to be +- * hard-wired to zero for downstream ports ++ * PCIe requires that the Clock Power Management capability bit ++ * is hard-wired to zero for downstream ports but HW returns 1. + */ + *value = mvebu_readl(port, PCIE_CAP_PCIEXP + PCI_EXP_LNKCAP) & + ~PCI_EXP_LNKCAP_CLKPM; +-- +2.34.1 + -- cgit v1.2.3