From 955268e13f8f9422e7e89ee6350ec793dddd1e94 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Karel=20Ko=C4=8D=C3=AD?= Date: Tue, 1 Nov 2022 09:44:59 +0100 Subject: nixos: try to fix Turris Omnia PCIe on Linux 6.0 Unfortunatelly this seems to not work. --- ...-irqchip-armada-370-xp-Update-information.patch | 42 ++++++++++++++++++++++ 1 file changed, 42 insertions(+) create mode 100644 nixos/modules/omnia-kernel-patches/0029-dt-bindings-irqchip-armada-370-xp-Update-information.patch (limited to 'nixos/modules/omnia-kernel-patches/0029-dt-bindings-irqchip-armada-370-xp-Update-information.patch') diff --git a/nixos/modules/omnia-kernel-patches/0029-dt-bindings-irqchip-armada-370-xp-Update-information.patch b/nixos/modules/omnia-kernel-patches/0029-dt-bindings-irqchip-armada-370-xp-Update-information.patch new file mode 100644 index 0000000..29bb342 --- /dev/null +++ b/nixos/modules/omnia-kernel-patches/0029-dt-bindings-irqchip-armada-370-xp-Update-information.patch @@ -0,0 +1,42 @@ +From 74acdb46ee1c31a4071bc25deaa6a9ed6e10229e Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Pali=20Roh=C3=A1r?= +Date: Fri, 6 May 2022 14:22:28 +0200 +Subject: [PATCH 29/53] dt-bindings: irqchip: armada-370-xp: Update information + about MPIC SoC Error +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Signed-off-by: Pali Rohár +--- + .../interrupt-controller/marvell,armada-370-xp-mpic.txt | 9 +++++++++ + 1 file changed, 9 insertions(+) + +diff --git a/Documentation/devicetree/bindings/interrupt-controller/marvell,armada-370-xp-mpic.txt b/Documentation/devicetree/bindings/interrupt-controller/marvell,armada-370-xp-mpic.txt +index 5fc03134a999..8cddbc16ddbd 100644 +--- a/Documentation/devicetree/bindings/interrupt-controller/marvell,armada-370-xp-mpic.txt ++++ b/Documentation/devicetree/bindings/interrupt-controller/marvell,armada-370-xp-mpic.txt +@@ -24,6 +24,11 @@ Optional properties: + connected as a slave to the Cortex-A9 GIC. The provided interrupt + indicate to which GIC interrupt the MPIC output is connected. + ++Optional subnodes: ++ ++- interrupt-controller@20 with interrupt-controller property for ++ MPIC SoC Error IRQ controller ++ + Example: + + mpic: interrupt-controller@d0020000 { +@@ -35,4 +40,8 @@ Example: + msi-controller; + reg = <0xd0020a00 0x1d0>, + <0xd0021070 0x58>; ++ soc_err: interrupt-controller@20 { ++ interrupt-controller; ++ #interrupt-cells = <1>; ++ }; + }; +-- +2.37.3 + -- cgit v1.2.3