From 213042bba186b995bc2f25c8c2d06a9652177fa3 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Karel=20Ko=C4=8D=C3=AD?= Date: Tue, 27 Sep 2022 17:09:49 +0200 Subject: Import Turris OS kernel patches --- ...k-Don-t-write-read-only-bits-explicitly-i.patch | 39 ++++++++++++++++++++++ 1 file changed, 39 insertions(+) create mode 100644 nixos/modules/kernel-patches/0026-PCI-aardvark-Don-t-write-read-only-bits-explicitly-i.patch (limited to 'nixos/modules/kernel-patches/0026-PCI-aardvark-Don-t-write-read-only-bits-explicitly-i.patch') diff --git a/nixos/modules/kernel-patches/0026-PCI-aardvark-Don-t-write-read-only-bits-explicitly-i.patch b/nixos/modules/kernel-patches/0026-PCI-aardvark-Don-t-write-read-only-bits-explicitly-i.patch new file mode 100644 index 0000000..0a248e4 --- /dev/null +++ b/nixos/modules/kernel-patches/0026-PCI-aardvark-Don-t-write-read-only-bits-explicitly-i.patch @@ -0,0 +1,39 @@ +From 3d3bb1ce67148f05ae3f42d9642bae8011919800 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Marek=20Beh=C3=BAn?= +Date: Thu, 18 Aug 2022 15:51:38 +0200 +Subject: [PATCH 26/96] PCI: aardvark: Don't write read-only bits explicitly in + PCI_ERR_CAP register +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +The bits PCI_ERR_CAP_ECRC_GENC and PCI_ERR_CAP_ECRC_CHKC are read only, +reporting the capability of ECRC. Don't write them explicitly, instead +read the register (where they are set), and add the bits that enable +these features. + +Signed-off-by: Marek Behún +--- + drivers/pci/controller/pci-aardvark.c | 6 +++--- + 1 file changed, 3 insertions(+), 3 deletions(-) + +diff --git a/drivers/pci/controller/pci-aardvark.c b/drivers/pci/controller/pci-aardvark.c +index 635f236232bb..93e2e0234df6 100644 +--- a/drivers/pci/controller/pci-aardvark.c ++++ b/drivers/pci/controller/pci-aardvark.c +@@ -584,9 +584,9 @@ static void advk_pcie_setup_hw(struct advk_pcie *pcie) + reg &= ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); + advk_writel(pcie, reg, PCIE_CORE_CMD_STATUS_REG); + +- /* Set Advanced Error Capabilities and Control PF0 register */ +- reg = PCI_ERR_CAP_ECRC_GENC | PCI_ERR_CAP_ECRC_GENE | +- PCI_ERR_CAP_ECRC_CHKC | PCI_ERR_CAP_ECRC_CHKE; ++ /* Enable generation and checking of ECRC on Root Bridge */ ++ reg = advk_readl(pcie, PCIE_CORE_PCIERR_CAP + PCI_ERR_CAP); ++ reg |= PCI_ERR_CAP_ECRC_GENE | PCI_ERR_CAP_ECRC_CHKE; + advk_writel(pcie, reg, PCIE_CORE_PCIERR_CAP + PCI_ERR_CAP); + + /* Set PCIe Device Control register */ +-- +2.37.2 + -- cgit v1.2.3