diff options
Diffstat (limited to 'pkgs/patches-linux-5.15/0101-PCI-aardvark-Don-t-write-read-only-bits-explicitly-i.patch')
-rw-r--r-- | pkgs/patches-linux-5.15/0101-PCI-aardvark-Don-t-write-read-only-bits-explicitly-i.patch | 39 |
1 files changed, 39 insertions, 0 deletions
diff --git a/pkgs/patches-linux-5.15/0101-PCI-aardvark-Don-t-write-read-only-bits-explicitly-i.patch b/pkgs/patches-linux-5.15/0101-PCI-aardvark-Don-t-write-read-only-bits-explicitly-i.patch new file mode 100644 index 0000000..edce284 --- /dev/null +++ b/pkgs/patches-linux-5.15/0101-PCI-aardvark-Don-t-write-read-only-bits-explicitly-i.patch @@ -0,0 +1,39 @@ +From 055c623c268ee0031d05c1346f9f4c24fe3f0846 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Marek=20Beh=C3=BAn?= <kabel@kernel.org> +Date: Thu, 18 Aug 2022 15:51:38 +0200 +Subject: [PATCH 2/2] PCI: aardvark: Don't write read-only bits explicitly in + PCI_ERR_CAP register +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +The bits PCI_ERR_CAP_ECRC_GENC and PCI_ERR_CAP_ECRC_CHKC are read only, +reporting the capability of ECRC. Don't write them explicitly, instead +read the register (where they are set), and add the bits that enable +these features. + +Signed-off-by: Marek BehĂșn <kabel@kernel.org> +--- + drivers/pci/controller/pci-aardvark.c | 6 +++--- + 1 file changed, 3 insertions(+), 3 deletions(-) + +diff --git a/drivers/pci/controller/pci-aardvark.c b/drivers/pci/controller/pci-aardvark.c +index a5b1ebfb9520..325c22092e16 100644 +--- a/drivers/pci/controller/pci-aardvark.c ++++ b/drivers/pci/controller/pci-aardvark.c +@@ -586,9 +586,9 @@ static void advk_pcie_setup_hw(struct advk_pcie *pcie) + reg &= ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); + advk_writel(pcie, reg, PCIE_CORE_CMD_STATUS_REG); + +- /* Set Advanced Error Capabilities and Control PF0 register */ +- reg = PCI_ERR_CAP_ECRC_GENC | PCI_ERR_CAP_ECRC_GENE | +- PCI_ERR_CAP_ECRC_CHKC | PCI_ERR_CAP_ECRC_CHKE; ++ /* Enable generation and checking of ECRC on Root Bridge */ ++ reg = advk_readl(pcie, PCIE_CORE_PCIERR_CAP + PCI_ERR_CAP); ++ reg |= PCI_ERR_CAP_ECRC_GENE | PCI_ERR_CAP_ECRC_CHKE; + advk_writel(pcie, reg, PCIE_CORE_PCIERR_CAP + PCI_ERR_CAP); + + /* Set PCIe Device Control register */ +-- +2.34.1 + |