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Diffstat (limited to 'pkgs/patches-linux-5.15/0053-PCI-mvebu-Use-devm_request_irq-for-registering-inter.patch')
-rw-r--r--pkgs/patches-linux-5.15/0053-PCI-mvebu-Use-devm_request_irq-for-registering-inter.patch99
1 files changed, 99 insertions, 0 deletions
diff --git a/pkgs/patches-linux-5.15/0053-PCI-mvebu-Use-devm_request_irq-for-registering-inter.patch b/pkgs/patches-linux-5.15/0053-PCI-mvebu-Use-devm_request_irq-for-registering-inter.patch
new file mode 100644
index 0000000..d09446f
--- /dev/null
+++ b/pkgs/patches-linux-5.15/0053-PCI-mvebu-Use-devm_request_irq-for-registering-inter.patch
@@ -0,0 +1,99 @@
+From 149b6e20ecbc96ede412736d5c26496382d382e7 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@kernel.org>
+Date: Tue, 24 May 2022 13:57:37 +0200
+Subject: [PATCH 53/90] PCI: mvebu: Use devm_request_irq() for registering
+ interrupt handler
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Same as in commit a3b69dd0ad62 ("Revert "PCI: aardvark: Rewrite IRQ code to
+chained IRQ handler"") for pci-aardvark driver, use devm_request_irq()
+instead of chained IRQ handler in pci-mvebu.c driver.
+
+This change fixes affinity support and allows to pin interrupts from
+different PCIe controllers to different CPU cores.
+
+Fixes: ec075262648f ("PCI: mvebu: Implement support for legacy INTx interrupts")
+Signed-off-by: Pali Rohár <pali@kernel.org>
+---
+ drivers/pci/controller/pci-mvebu.c | 30 +++++++++++++++++-------------
+ 1 file changed, 17 insertions(+), 13 deletions(-)
+
+diff --git a/drivers/pci/controller/pci-mvebu.c b/drivers/pci/controller/pci-mvebu.c
+index 8205b4d1f04c..d8cba09649ba 100644
+--- a/drivers/pci/controller/pci-mvebu.c
++++ b/drivers/pci/controller/pci-mvebu.c
+@@ -1097,16 +1097,13 @@ static int mvebu_pcie_init_irq_domain(struct mvebu_pcie_port *port)
+ return 0;
+ }
+
+-static void mvebu_pcie_irq_handler(struct irq_desc *desc)
++static irqreturn_t mvebu_pcie_irq_handler(int irq, void *arg)
+ {
+- struct mvebu_pcie_port *port = irq_desc_get_handler_data(desc);
+- struct irq_chip *chip = irq_desc_get_chip(desc);
++ struct mvebu_pcie_port *port = arg;
+ struct device *dev = &port->pcie->pdev->dev;
+ u32 cause, unmask, status;
+ int i;
+
+- chained_irq_enter(chip, desc);
+-
+ cause = mvebu_readl(port, PCIE_INT_CAUSE_OFF);
+ unmask = mvebu_readl(port, PCIE_INT_UNMASK_OFF);
+ status = cause & unmask;
+@@ -1120,7 +1117,7 @@ static void mvebu_pcie_irq_handler(struct irq_desc *desc)
+ dev_err_ratelimited(dev, "unexpected INT%c IRQ\n", (char)i+'A');
+ }
+
+- chained_irq_exit(chip, desc);
++ return status ? IRQ_HANDLED : IRQ_NONE;
+ }
+
+ static int mvebu_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
+@@ -1580,9 +1577,20 @@ static int mvebu_pcie_probe(struct platform_device *pdev)
+ mvebu_pcie_powerdown(port);
+ continue;
+ }
+- irq_set_chained_handler_and_data(irq,
+- mvebu_pcie_irq_handler,
+- port);
++
++ ret = devm_request_irq(dev, irq, mvebu_pcie_irq_handler,
++ IRQF_SHARED | IRQF_NO_THREAD,
++ port->name, port);
++ if (ret) {
++ dev_err(dev, "%s: cannot register interrupt handler: %d\n",
++ port->name, ret);
++ irq_domain_remove(port->intx_irq_domain);
++ pci_bridge_emul_cleanup(&port->bridge);
++ devm_iounmap(dev, port->base);
++ port->base = NULL;
++ mvebu_pcie_powerdown(port);
++ continue;
++ }
+ }
+
+ /*
+@@ -1689,7 +1697,6 @@ static int mvebu_pcie_remove(struct platform_device *pdev)
+
+ for (i = 0; i < pcie->nports; i++) {
+ struct mvebu_pcie_port *port = &pcie->ports[i];
+- int irq = port->intx_irq;
+
+ if (!port->base)
+ continue;
+@@ -1705,9 +1712,6 @@ static int mvebu_pcie_remove(struct platform_device *pdev)
+ /* Clear all interrupt causes. */
+ mvebu_writel(port, ~PCIE_INT_ALL_MASK, PCIE_INT_CAUSE_OFF);
+
+- if (irq > 0)
+- irq_set_chained_handler_and_data(irq, NULL, NULL);
+-
+ /* Remove IRQ domains. */
+ if (port->intx_irq_domain)
+ irq_domain_remove(port->intx_irq_domain);
+--
+2.34.1
+