From 401d8ce02e0638f96d66b9ac1f0b43219b2d20d2 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Karel=20Ko=C4=8D=C3=AD?= <cynerd@email.cz>
Date: Sat, 14 Mar 2015 11:37:43 +0100
Subject: SPI implemented !NOT TESTED!

SPI for spi hardware implemented, but newer tested yet!
---
 src/avr5/spi.c | 47 +++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 47 insertions(+)
 create mode 100644 src/avr5/spi.c

(limited to 'src')

diff --git a/src/avr5/spi.c b/src/avr5/spi.c
new file mode 100644
index 0000000..bc026ef
--- /dev/null
+++ b/src/avr5/spi.c
@@ -0,0 +1,47 @@
+#include "../../spi.h"
+
+#if __AVR_ARCH__ == 5
+
+inline void ioe_spi_join(void) {
+    // TODO
+}
+
+#ifdef IOE_SPI_MASTER
+inline void ioe_spi_init(void) {
+    // Set MOSI and SCK output, all other input
+    DDR_SPI = _BV(DD_MOSI) | _BV(DD_SCLK);
+    // Enable interrupt
+    SPCR |= _BV(SPIE);
+    // Enable SPI master and set clock rate fck/16
+    SPCR = _BV(SPE) | _BV(MSTR) | _BV(SPR0);
+}
+
+inline int ioe_spi_ready(void) {
+    // TODO
+}
+
+inline void ioe_spi_transfer(int8_t data) {
+    SPDR = data;
+}
+
+#else /* IOE_SPI_MASTER */
+inline void ioe_spi_init(void) {
+    // Set MISO as output, all other input
+    DDR_SPI = _BV(DD_MISO);
+    // Enable interrupt
+    SPCR |= _BV(SPIE);          
+    // Enable SPI
+    SPCR = _BV(SPE);
+}
+
+inline void ioe_spi_expose(int8_t data) {
+    SPDR = data;
+}
+
+#endif /* IOE_SPI_MASTER */
+
+SIGNAL(SPI_STC_vect) {
+    ioe_spi_retrieve(SPDR);
+}
+
+#endif /* __AVR_ARCH__ == 5 */
-- 
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