From 5d29fe79d30f430ae326d9dc57ccfaed6fe61328 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Karel=20Ko=C4=8D=C3=AD?= Date: Tue, 8 Mar 2016 16:10:33 +0100 Subject: Another full update of current work --- include/spi.h | 66 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 66 insertions(+) create mode 100644 include/spi.h (limited to 'include/spi.h') diff --git a/include/spi.h b/include/spi.h new file mode 100644 index 0000000..8d51eb9 --- /dev/null +++ b/include/spi.h @@ -0,0 +1,66 @@ +#include +#include +#include + +#include "mcu/mcu_def.h" +#include "tasks.h" + +#ifndef _IOE_SPI_H_ +#define _IOE_SPI_H_ +#ifdef CONFIG_SPI + +enum spiMode { + SPI_MODE_MASTER, + SPI_MODE_SLAVE +}; + +volatile extern int8_t _spi_busy; +volatile extern Mutex spi_mutex; + +static inline void spi_init(enum spiMode mode) { + _spi_busy = 0; + if (mode == SPI_MODE_MASTER) { + // Set MOSI and SCK output + DDR_SPI |= _BV(DD_MOSI) | _BV(DD_SCLK); + // Set MISO pull up resistor + PORT_SPI |= _BV(PORT_MISO); + // Enable SPI master, set clock rate fck/16 and enable SPI interrupt + SPCR = _BV(SPE) | _BV(SPIE) | _BV(MSTR) | _BV(SPR0); + } else { + // Set MISO as output + DDR_SPI |= _BV(DD_MISO); + // Set SCLK and MOSI pull up resistor + PORT_SPI |= _BV(PORT_SCLK) | _BV(PORT_MOSI); + // Enable SPI and interrupt + SPCR = _BV(SPE) | _BV(SPIE); + } +} + +static inline int8_t spi_busy(void) { + return _spi_busy; +} + +static inline void spi_join(void) { + task_delay_till(&_spi_busy, 0); +} + +static inline void spi_transfer(uint8_t data) { + _spi_busy = 1; + SPDR = data; +} + +static inline uint8_t spi_send(uint8_t data) { + spi_transfer(data); + task_delay_till(&_spi_busy, 0); + return SPDR; +} + +static inline void spi_expose(uint8_t data) { + SPDR = data; +} + +// Null terminated array +extern void (*spi_receive)(uint8_t data); + +#endif /* CONFIG_SPI */ +#endif /* _IOE_SPI_H_ */ -- cgit v1.2.3