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author | Karel Kočí <cynerd@email.cz> | 2015-10-11 13:06:28 +0200 |
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committer | Karel Kočí <cynerd@email.cz> | 2015-10-11 13:06:28 +0200 |
commit | bab75a6068ab0a64fe22395ad11efafccbf0d842 (patch) | |
tree | 59344457d25c2e72904acac20118eb16633908fe /src/spi.c | |
parent | 1b0b3cb1b61759be5c2e100d08c84e5eec924a58 (diff) | |
download | avr-ioe-bab75a6068ab0a64fe22395ad11efafccbf0d842.tar.gz avr-ioe-bab75a6068ab0a64fe22395ad11efafccbf0d842.tar.bz2 avr-ioe-bab75a6068ab0a64fe22395ad11efafccbf0d842.zip |
Implement SPI and remove files
Diffstat (limited to 'src/spi.c')
-rw-r--r-- | src/spi.c | 66 |
1 files changed, 36 insertions, 30 deletions
@@ -1,48 +1,54 @@ #include "../spi.h" -#include "mcu/mcu_def.h" -inline void ioe_spi_join(void) { - // TODO +volatile int8_t _spi_busy; + +inline void spi_init(enum spiMode mode) { + _spi_busy = 0; + if (mode == SPI_MODE_MASTER) { + // Set MOSI and SCK output + DDR_SPI |= _BV(DD_MOSI) | _BV(DD_SCLK); + // Set MISO pull up resistor + PORT_SPI |= _BV(PORT_MISO); + // Enable SPI master, set clock rate fck/16 and enable SPI interrupt + SPCR = _BV(SPE) | _BV(SPIE) | _BV(MSTR) | _BV(SPR0); + } else { + // Set MISO as output + DDR_SPI |= _BV(DD_MISO); + // Set SCLK and MOSI pull up resistor + PORT_SPI |= _BV(PORT_SCLK) | _BV(PORT_MOSI); + // Enable SPI and interrupt + SPCR = _BV(SPE) | _BV(SPIE); + } } -inline int ioe_spi_bussy(void) { - // TODO +inline int8_t spi_busy(void) { + return _spi_busy; } -#ifdef IOE_SPI_MASTER -inline void ioe_spi_init(void) { - // Set MOSI and SCK output - DDR_SPI |= _BV(DD_MOSI) | _BV(DD_SCLK); - // Set MISO pull up resistor - PORT_SPI |= _BV(PORT_MISO); - // Enable SPI interrupt - SPCR |= _BV(SPIE); - // Enable SPI master and set clock rate fck/16 - SPCR = _BV(SPE) | _BV(MSTR) | _BV(SPR0); +inline void spi_join(void) { + while (spi_busy()); } -inline void ioe_spi_transfer(int8_t data) { - SPDR = data; +inline uint8_t spi_send(uint8_t data) { + spi_transfer(data); + while (spi_busy()); + return SPDR; } -#else /* IOE_SPI_MASTER */ -inline void ioe_spi_init(void) { - // Set MISO as output - DDR_SPI = _BV(DD_MISO); - // Set SCLK and MOSI pull up resistor - PORT_SPI |= _BV(PORT_SCLK) | _BV(PORT_MOSI); - // Enable SPI interrupt - SPCR |= _BV(SPIE); - // Enable SPI - SPCR = _BV(SPE); +inline void spi_transfer(uint8_t data) { + _spi_busy = 1; + SPDR = data; } -inline void ioe_spi_expose(int8_t data) { +inline void spi_expose(uint8_t data) { SPDR = data; } -#endif /* IOE_SPI_MASTER */ +////// Interrupts //////////////////////////////// +void (*spi_receive)(uint8_t data) = 0; SIGNAL(SPI_STC_vect) { - ioe_spi_retrieve(SPDR); + _spi_busy = 0; + if (spi_receive) + spi_receive(SPDR); } |