aboutsummaryrefslogtreecommitdiff
path: root/src/avr5
diff options
context:
space:
mode:
authorKarel Kočí <cynerd@email.cz>2015-03-14 11:37:43 +0100
committerKarel Kočí <cynerd@email.cz>2015-03-14 11:37:43 +0100
commit401d8ce02e0638f96d66b9ac1f0b43219b2d20d2 (patch)
tree0a11ccfbb368be80253e658b9054ebde684e0d60 /src/avr5
parent8a115123eee5b9e294ff86ec4e41e6112dc47774 (diff)
downloadavr-ioe-401d8ce02e0638f96d66b9ac1f0b43219b2d20d2.tar.gz
avr-ioe-401d8ce02e0638f96d66b9ac1f0b43219b2d20d2.tar.bz2
avr-ioe-401d8ce02e0638f96d66b9ac1f0b43219b2d20d2.zip
SPI implemented !NOT TESTED!
SPI for spi hardware implemented, but newer tested yet!
Diffstat (limited to 'src/avr5')
-rw-r--r--src/avr5/spi.c47
1 files changed, 47 insertions, 0 deletions
diff --git a/src/avr5/spi.c b/src/avr5/spi.c
new file mode 100644
index 0000000..bc026ef
--- /dev/null
+++ b/src/avr5/spi.c
@@ -0,0 +1,47 @@
+#include "../../spi.h"
+
+#if __AVR_ARCH__ == 5
+
+inline void ioe_spi_join(void) {
+ // TODO
+}
+
+#ifdef IOE_SPI_MASTER
+inline void ioe_spi_init(void) {
+ // Set MOSI and SCK output, all other input
+ DDR_SPI = _BV(DD_MOSI) | _BV(DD_SCLK);
+ // Enable interrupt
+ SPCR |= _BV(SPIE);
+ // Enable SPI master and set clock rate fck/16
+ SPCR = _BV(SPE) | _BV(MSTR) | _BV(SPR0);
+}
+
+inline int ioe_spi_ready(void) {
+ // TODO
+}
+
+inline void ioe_spi_transfer(int8_t data) {
+ SPDR = data;
+}
+
+#else /* IOE_SPI_MASTER */
+inline void ioe_spi_init(void) {
+ // Set MISO as output, all other input
+ DDR_SPI = _BV(DD_MISO);
+ // Enable interrupt
+ SPCR |= _BV(SPIE);
+ // Enable SPI
+ SPCR = _BV(SPE);
+}
+
+inline void ioe_spi_expose(int8_t data) {
+ SPDR = data;
+}
+
+#endif /* IOE_SPI_MASTER */
+
+SIGNAL(SPI_STC_vect) {
+ ioe_spi_retrieve(SPDR);
+}
+
+#endif /* __AVR_ARCH__ == 5 */