qtmips/qtmips_machine/tests, branch masterMIPS CPU emulator for education purposeshttp://git.cynerd.cz/qtmips/atom?h=master2019-03-26T22:40:21ZChange single cycle core with delay slot to use separate fetch stage.2019-03-26T22:40:21ZPavel Pisapisa@cmp.felk.cvut.cz2019-03-26T22:40:21Zurn:sha1:c72e3ad5824eb9385b62a51633cff817b825f06d
When instructions are visualized then it is even more
misleading to keep old instruction in decode phase delay buffer.
The single cycle core with delay slot is upgraded
to the variant with fetch and execute phases.
This way the structure is logical and delay slot
has purpose.
Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
Correct write through spelling. Reported by Richard Susta.2019-03-25T14:26:32ZPavel Pisapisa@cmp.felk.cvut.cz2019-03-25T14:25:59Zurn:sha1:9713d030bb1696269c3348cac83e13306edd65cf
Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
Make use of QVERIFY_EXCEPTION_THROWN conditional, it is not available on Ubuntu Trusty.2019-03-15T14:55:29ZPavel Pisapisa@cmp.felk.cvut.cz2019-03-15T14:55:29Zurn:sha1:ff306d57f2217a878c6a700915a30dd574522a40
Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
Switch to static libraries by default and ensure application rebuild when a library changes.2019-03-15T08:37:35ZPavel Pisapisa@cmp.felk.cvut.cz2019-03-15T08:37:35Zurn:sha1:df8f379ac98ec8ddfafde57f211959e3073fc0de
I have not found a way how to pass additional CONFIG options
to Debian package build (dpkg-buildpackage) when qmake is invoked from
debian/rules with debian helper based (dh) build.
The way how qmake solves dependencies between program and libraries
comes from stone age. It is necessary to include complete path
to the library in PRE_TARGETDEPS definition including lib prefix
and .a suffix. This is non portable and cannot be easily used
when static and dynamic libraries build alternatives are considered.
Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
Fix LB and LH sign extension and LH/SH mask calculation.2019-03-13T12:53:30ZPavel Pisapisa@cmp.felk.cvut.cz2019-03-13T12:53:30Zurn:sha1:4637416160771a6357bd8bebf61626ca599c500b
Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
Added test for LWR, LWL, SWR and SWL instructions.2019-02-21T12:57:10ZPavel Pisapisa@cmp.felk.cvut.cz2019-02-21T12:57:10Zurn:sha1:1079afe82fae73f1ee61266b0b573b95e8c1ce48
The reference data has been obtained by running application
under userspace MIPS QEMU.
Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
Distinguish between write-through cache with allocate and update only if hit.2019-02-20T13:17:32ZPavel Pisapisa@cmp.felk.cvut.cz2019-02-20T13:17:32Zurn:sha1:adb9f147e358f687b37f5bf14c68f559c7c86a79
Add into cache statistic number of backing/main memory accesses.
Correction of meaning and computation of the cache statistic.
Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
Update project files to adapt for release and debug libraries location for Windows builds.2019-02-19T11:27:52ZPavel Pisapisa@cmp.felk.cvut.cz2019-02-19T11:27:52Zurn:sha1:b01f4f6c24ed6ff80f822d6ed546c188655bda27
Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
Pass arithmetic exception trough pipeline and implement trap support and instructions.2019-02-17T20:15:53ZPavel Pisapisa@cmp.felk.cvut.cz2019-02-17T20:15:53Zurn:sha1:9d82517dea100d94fd8d0d5326ca5db7b5a1e595
Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
Implement EXT instruction used in GLIBC startup.2019-02-15T14:23:56ZPavel Pisapisa@cmp.felk.cvut.cz2019-02-15T14:23:56Zurn:sha1:eb217996098ffb5706cfe0ca8ffa4478b73ceb8e
It requires one more field to pass to ALU.
Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>