qtmips, branch simple-memory-view MIPS CPU emulator for education purposes http://git.cynerd.cz/qtmips/atom?h=simple-memory-view 2018-03-06T21:08:53Z WIP: simplify memory view 2018-03-06T21:08:53Z Karel Kočí cynerd@email.cz 2018-03-06T21:08:53Z urn:sha1:e6c3d5bdc7a4763bd6816d52b0d1b42a7e4b08f1 This removes problematic buffer zone of memory view. Instead we will use no buffer zone and load needed elements as soon as possible. Append some TODOs 2018-03-06T21:07:34Z Karel Kočí cynerd@email.cz 2018-03-06T21:07:34Z urn:sha1:e869534670e1e1cb3b68c1e60205c36dff2dcb16 Fix forwarding checker for I and J and S* instructions 2018-03-06T20:58:49Z Karel Kočí cynerd@email.cz 2018-02-16T15:24:35Z urn:sha1:1a20d908b6eefe32807f906b7294c562256a7518 THere are exceptions when we care about forwarding and when we don't. Implement Cache configuration 2018-03-06T20:57:07Z Karel Kočí cynerd@email.cz 2018-03-06T20:57:07Z urn:sha1:a56b25212865c57251719a1d4a5d9d6a79b339c5 This commit implements both cache configuration for machine and for gui. Forward from execute stage to decode stage latch 2018-02-14T13:40:18Z Karel Kočí cynerd@email.cz 2018-02-14T13:40:18Z urn:sha1:c75024c81ba92efbcc70e80520599a27b4aff0d8 Do empty fetch stage to report fetch even if we stall 2018-02-14T13:10:18Z Karel Kočí cynerd@email.cz 2018-02-14T13:10:18Z urn:sha1:98153a4f7b1edbd465a24d703016978e91cb14db Another swap in instruction decoding 2018-02-14T13:02:59Z Karel Kočí cynerd@email.cz 2018-02-14T13:02:59Z urn:sha1:31db65e43406dcafe5d2987587352e965f6b5171 Swap rs and rt in I instructons decoding 2018-02-14T12:51:53Z Karel Kočí cynerd@email.cz 2018-02-14T12:51:53Z urn:sha1:1f20805dfd189bd28a9b7b2f97ec3569096adad1 Fix signextend in core 2018-02-14T12:40:48Z Karel Kočí cynerd@email.cz 2018-02-14T12:40:48Z urn:sha1:a3faaa12e433a8ac4d82b481c276eb15039dc140 Fix program loading 2018-02-14T12:01:34Z Karel Kočí cynerd@email.cz 2018-02-14T12:01:34Z urn:sha1:b416eb2efdc82a1cd9b1b69b7f335750a725f738 First section was ignored